Hello Sylvia,

 

My general advice is to concentrate on any tests where the existing design
passed the specified requirements with minimal margin.

 

It is unlikely that alternate memory chips would require new safety testing. 
I can conceive of circumstances where you would have a product that marginally
passed a heating test and the new memory ICs consumed more power, but this is
a long shot.  You would need to have a lot of these ICs in the design before
they could contribute significantly to power consumption and dissipation.  If
you have only a few of these ICs, it is unlikely that safety would be an
issue.  

 

You may consider running a new radiated emissions test, but the need may
depend on numerous factors.  If the new memory ICs have significantly smaller
feature sizes, the edge rates could be noticeably faster leading to higher
emissions.  However, the new testing may not uncover issues unless the
original device was close to the limit due to noise from the memory ICs.  It
is unlikely that new memory chips would generate enough noise below 30 MHz
that would couple through a power supply, thereby requiring new conducted
emissions testing.

 

It can be harder to determine if the new memory chips will affect immunity
test results.  The new ICs may have a more sensitive reset line for example. 
Your existing design may tolerate some noise on reset, while the new memory
chips would not.  This could be a problem during ESD or possibly EFT.  My
personal experience has been that many of the other immunity tests are less
likely to be affected by alternate memory chips.

 

If your software plays any role in the product’s safety, I would have a
different recommendation.  In that case, I recommend that you run the complete
set of immunity tests.  You don’t want the risk of different memory behavior
affecting the system adversely.  In this case, you may need to consider a new
round of all tests, not just immunity.

 

Regards,

Ted Eckert

Compliance Engineer

Microsoft Corporation

[email protected]

 

The opinions expressed are my own and do not necessarily reflect those of my
employer.

 

 

 

From: Sylvia Toma [mailto:[email protected]] 
Sent: Wednesday, June 10, 2009 11:41 AM
To: [email protected]
Subject: end-product testing

 

Dear experts,

 

Could you shed some light as to what type of tests or checking one might do in
an end product when qualifying alternate memory chips (SDRAM, DRAM, etc.)?

 

Memory vendors generally do their own functional testing before product is
shipped.  Functional tests usually include VCC speed verification, VCC margin,
VCC bump, Dynamic and static research and a full range of array exercising
algorithms. As much as this is being done, we still see occasional failures in
end-product due to manufacturing defect of the chip or process breakdown at
the chip manufacturing location.

 

I'm looking forward to your guidance.

 

Regards

Sylvia

 

 

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