Similar articles, but somewhat different view: http://www.ti.com/lit/an/scaa120a/scaa120a.pdf https://www.maximintegrated.com/en/app-notes/index.mvp/id/4466
'Jitter' is both a specification and a measurement method that is specific to the equipment and the protocol. Its use for EMC characterization is different than its use for design verification of data systems. See 'clock tree' and 'spread spectrum' for two views. Am guessing that required RBW is linked to dynamic range of the information transfer rate in the signal, not just the data clock rate or carrier freq. Am certainly not an expert on the subject, but of the two sources of rate of change, one source will be a periodic that has a statistically-mapped variance around the design spec (the clock freq), which is deterministic. 'Random' jitter, when mapped with a big enough data set, will also appear to be deterministic; that is, will have a gausian distribution. So you will probably have change rates that map to bi-modal data, but are still both rate-delimited by probability distributions. And do not confuse jitter with latency. You can find articles that talk about data packet jitter - this is actually the variance of latency, and is not a principle contributer to the data rate jitter from the clock or carrier variance. FWIW, rate of change of jitter (jerk?) can be sometimes be inferred by the amplitude distributions of the modulation that is causing jitter. This is used by some clock recovery schemes. The problem with EMC stuff is that we are going back and forth from the frequency domain to the time domain to the phase domain at least twice. So you are looking at a purely statistical variance that can be used to provide probability of a rate of change for jitter. Brian From: Ken Javor [mailto:[email protected]] Sent: Wednesday, May 25, 2016 3:54 PM To: [email protected] Subject: Re: [PSES] Question regarding clock jitter specification The cited article was very interesting as to how to measure Jitter, but it did not answer the questions I posed as to how clock jitter is spec'd and how fast it changes (analogous to fm deviation and rate of deviation). This is not CISPR, it is measurements in band to specific radios with specific channel bandwidths, and the issue is to properly specify a measurement BW, and what happens when the measurement BW is improperly specified (measurement BW < radio channel BW). Ken Javor Phone: (256) 650-5261 ________________________________________ From: "Pawson, James" <[email protected]> Reply-To: "Pawson, James" <[email protected]> Date: Wed, 25 May 2016 09:42:55 +0000 To: <[email protected]> Conversation: Question regarding clock jitter specification Subject: Re: [PSES] Question regarding clock jitter specification Ken, Jitter can be a very complicated subject; we once received a detailed and complex presentation from LeCroy (now Teledyne) on the different types of jitter and how you could separate them out from each other e.g. random jitter, deterministic jitter, etc. It had more pictures and detail than this document - http://cdn.teledynelecroy.com/files/whitepapers/wp_jittermeasurement_in_serialdatasignals.pdf - but it gives you the flavour. Generally jitter seems to be defined as a maximum deviation from an ideal clock rate (e.g. 0.25 x T_bit for HDMI). The ideal clock could be either a recovered clock in the case of a serial link (like HDMI or SATA) or a clock that is transmitted in parallel to the signal (like PCIe). Introduce spread spectrum clocking in there and measurement becomes even more interesting! For the frequencies that you refer to, I believe CISPR defines a measurement bandwidth of 1MHz so I'm not sure why someone would me measuring with such a RBW unless it was specifically mentioned in a standard. You might hope that excessive jitter would make these higher harmonics a little lower in amplitude ;) James From: Ken Javor [mailto:[email protected]] Sent: 25 May 2016 04:20 To: [email protected] Subject: [PSES] Question regarding clock jitter specification What is a typical clock jitter specification? Is it given as a percentage of clock period? If not, how? Given some maximum jitter spec, how quickly does the clock period change? Can it go from no jitter to maximum deviation in one clock cycle? If so, is that typical? Or is it more typical to stay much closer to nominal than the jitter spec allows for many clock cycles, and then slowly deviate? These questions are asked not from a signal integrity vantage point, but rather that of EMC. In particular, I am concerned about people using very narrow measurement BWs to measure radiated emissions in microwave bands where the measurement is that of a clock harmonic, and thus the spreading of the clock jitter residual frequency modulation at the fundamental by the harmonic order. So for instance, if someone uses a 1 kHz BW at 10 GHz and expects to accurately measure the full value of a cw tone that is the harmonic of a lower frequency clock, the implication is that the jitter is less than 1e-7 of the clock period which will be much less than 1 ps even with a 10 MHz clock. If the jitter exceeds this value and actual radio protected by the RE measurement has a larger BW than that used in the RE measurement, then if the harmonic is quickly wandering in and out of the measurement pass band, it will be averaged in a way not representative of what the actual radio would see. Hence, the questions. Thank you, Ken Javor Phone: (256) 650-5261 - ---------------------------------------------------------------- This message is from the IEEE Product Safety Engineering Society emc-pstc discussion list. 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