"Peter C. Wallace" <[EMAIL PROTECTED]> wrote:
> Finally had a bit of free time to work on this. Still needs testing and more
> features but here whats there so far:
Is the VHDL for this going to be made available under the GPL? If so, I'm
interested in writing the HAL driver for it.
> 12 step gens. Each stepgen is 28 bit DDS + FIFO + preset/residue clear logic
>
> Step gens overlaid on basic I/O port, Step generators can be individually
> enabled, or I/O pins left as simple I/O. So for example if the stepgens are
> all disabled you have a 72 bit I/O port.
>
> Step/DIR or quadature output selectable per generator.
Nice. I think quadrature is far superior to step/dir. Its a shame the
stepper drive manufacturers don't agree.
On the step/dir side: some drives require setup and/or hold times for the
dir line with respect to the step line. Others have minumum step pulse
lengths. Do the generators support this? Min pulse length isn't that hard,
but setup and hold time can be a pain.
Example: You were running along at +10 steps/sec, then you switch to -10
steps/sec. 99.999% of the time that is fine. But if you make the change
a microsecond after the DDS has generated an "up" step, it will want to
generate a "down" step a microsecond later. (The DDS accumulator will
have only added a tiny amount, so once you switch directions, it will only
have to subtract a tiny amount.) The HAL software stepgen has more code
(crufty code at that) to ensure setup and hold times than is required for
the DDS itself.
> Step gens are buffered (16 deep x 32 bit wide FIFOs each). This means that
> real time is not required (at least for step generation), For example at a
> basic clock of 8 MHz and a frame size (frame size is how many additions are
> done to step generator DDS per FIFO entry) of 8000, the step gen will consume
> one FIFO entry per mSec. Since the FIFOs are 16 deep, if we use interrupts or
> just poll the FIFOhalf full register the interrupt latency or minimum polling
> time would ge 8 mSec (125 Hz).
For some applications this might be a feature. For EMC its a bug. We
already have hard realtime code, and the system time base comes from the
realtime threads in the PC, not from the FPGA.
Do the step-generators provide access to the value of the DDS accumulator,
and/or a cumulative count of steps issued? If so we can close a loop around
the stepgen. Or does it rely on the fact that each value in the FIFO will
be added to the DDS accumulator _exactly_ some known number of times? If
the latter is the case, then you are requiring the software to synchronize
itself to the hardware.
In some applications a hardware determined "frame" is exactly what the
doctor ordered, and the software can be synced to it easily. But what
happens when two or more hardware devices are in use, and both expect to
be able to generate the "frame" times for the application? EMC to date
has chosen to let the software determine the frame timing - the period
of the servo thread is our "frame".
> Also the basic local bus interface has been changed to be 32 bit memory
> only, and has support for burst transfer mode.
That sounds promizing.
> Things to do:
>
> Add quadrature counters (probably just graft in existing one)
>
> Add simplified PWM gens (no fancy signed/unsigned modes)
>
> Add SPI channels (for general use plus for our I/O expander and 7I41 stepper
> interface use SPI)
>
>
> Peter Wallace
> Mesa Electronics
>
> (\__/)
> (='.'=) This is Bunny. Copy and paste bunny into your
> (")_(") signature to help him gain world domination.
Long live the bunny!
It is possible that EMC and non-EMC related applications of the 5i20 don't
want the same feature sets. I'd like to go into more detail with you
regarding EMC/HAL drivers and configurations for the 5i20. I'm not sure the
users list is the ideal place for some of the more arcane FPGA stuff - maybe
the developers list would be better.
I have a couple of 5i20 boards (one for my CNC project, one for development),
and I have a number of specific things I want to do with them. All VHDL code
and/or drivers that I write will be released under the GPL.
Regards,
John Kasunich
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