On Monday 03 August 2015 00:41:09 John Kasunich wrote: > On Sun, Aug 2, 2015, at 08:18 PM, Andy Pugh wrote: > > > On 3 Aug 2015, at 00:21, John Kasunich <[email protected]> > > > wrote: > > > > > > So he > > > gets velocity jitter. He's trying to make a 4 sample moving > > > average, since the jitter should cancel out over a full quadrature > > > cycle. > > > > I don't plan to do it, but I can see good arguments for that being > > the way that the encoder component did it. > > Well, if you have a good encoder, the existing encoder algorithm has > less lag. Not an issue at high speeds with high ppr encoders, but > potentially a problem at the low end. I wouldn't change the existing > algorithm. > > I like your idea of using a second encoder comp in counter mode. I'm > 99% sure that mode always looks at the same edge, so it should reduce > velocity jitter by the same amount that Gene's arrangement will. Easy > enough to try with halscope looking at the velocity outputs of both > encoders as well as Gene's arrangement.
The discussion is nice, but it still doesn't get me a signal I can strobe the .hold lines with. This is what I have written so far: gene@GO704:~/linuxcnc/configs/GO704fast$ cat encoder_filter.hal # this is a sample outline of an encoder filter to reduce noise from # imperfections in in the optical disk, and from sample quantization. loadrt sample_hold names=enc0,enc1,enc2,enc3 loadrt sum2 names=sum01,sum23,sumenc # arrange these to save the previous modules state, # otherwise it cascades thru in one cycle addf enc3 servo-thread # so it saves enc2's output addf enc2 servo-thread # so it saves enc1's output addf enc1 servo-thread # so it saves enc0's output addf enc0 servo-thread # so it saves encoder velocity addf sum01 servo-thread # now total it up addf sum23 servo-thread # ditto addf sumenc servo-thread # ditto setp sumenc.gain0 .25 # scale it back to unity setp sumenc.gain1 .25 # scale it back to unity net encfilter_in hm2_5i25.0.encoder.00.velocity-out enc0.in # feed enc0 net filter-1 enc0.out enc1.in sum01.in0 # link output net filter-2 enc1.out enc2.in sum01.in1 # link output net filter-3 enc2.out enc3.in sum23.in0 # link output net filter-4 enc3.out sum23.in1 # link output net filter-5 sum01.out sumenc.in0 # put it all together net filter-6 sum23.out sumenc.in1 # put it all together net spndl-velocity sumenc.out # to where ever needed This of course needs to be broken up and inserted in the main hal file in the appropriate locations. So I'll setp the .hold lines for all (false) thru which should give the desired shift if the addf orders are reversed. The manpage for sample_hold make no suggestion as to how to handle the hold/sample signal. Concise is nice, but not when it leaves out important data. Anyway, its the middle of the night & I need some more z's. Thanks guys. Cheers, Gene Heskett -- "There are four boxes to be used in defense of liberty: soap, ballot, jury, and ammo. Please use in that order." -Ed Howdershelt (Author) Genes Web page <http://geneslinuxbox.net:6309/gene> ------------------------------------------------------------------------------ _______________________________________________ Emc-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/emc-users
