This message is from the T13 list server.
The APIC or IOAPIC basically gives a PC more than the 16 legacy interrupts. There can be boot issues if more than 1 boot device is tied to an interrupt. APIC is the most popular method that has been used to expand the interrupt structure. When you move to the APIC environment, you are also expected to move away from having many devices tied to a single interrupt. Some parts of the APIC configuration are chipset specifiec. I think ACPI provides some mechanisms for working with the APIC. Click on http://www.microsoft.com/whdc/hwdev/bus/pci/ACPI-MP.mspx to get some of the information on how ACPI works with the APIC. ------------------------------------------------ Curtis E. Stevens 29 Dewey Irvine, Ca. 92620 Home Phone: 949-552-4777 Cell: 949-307-5050 E-Mail: [EMAIL PROTECTED] ----- Original Message ----- From: "Hale Landis" <[EMAIL PROTECTED]> To: <[EMAIL PROTECTED]> Sent: Tuesday, February 17, 2004 11:49 AM Subject: Re: [t13] o x3F6 DeviceControl default should be what > This message is from the T13 list server. > > > On 17 Feb 2004 09:37:18 -0700, Pat LaVarre wrote: > >This message is from the T13 list server. > > >At my desk now, I see o 376 02 floats INTRQ hi, just as selecting the > >absent device vi o 1F6 does. > > Yes, tradition INTRQ signals like ATA are tri-state, may float high > or low, by in a traditional PC design only the low to high edge means > anything. > > >> Well the possible values are: > >> 80H - HOB bit (ATA devices) > >> 04H - SRST bit > >> 02H - nIEN bit > >Please could you elaborate "possible"? > > All the other bits are reserved (have no definition and should be > written as 0 by a host). > > >> NOTE: Bit 0 shall always be written by a host as zero. > >Mask x01 used to mean something? > > No, it is an old PC thing, I think it was a bit shared with the > floppy controller. > > >By its t13.org definition, the o x3F6 DeviceControl port is shared and > >write-only. That means I can't read it, mess with it, restore it. > > Correct. > > >Instead, when I need to force x02 nIEN lo for my device under test, I > >have to guess what else may have been written in the other bits or for > >the sake of the other device on the bus. > > If you look at the other (non-reserved) bits it really doesn't matter > what the last value was. > > HOB would only be on while the LBA48 values are being read back from > the device. SRST would only be on if Soft Reset was starting. Since > virtuall all software writes DevCtrl at the begining of every command > the nIEN value really doesn't mean anything either. > > >Are we not now starting to see x80 and x82 grow common? > > See the description of HOB (that 80H bit). I think you can ignore it. > > >> especially for > >> read commands that do not transfer all the data described by the DMA > >> PRD list. > >This means the host can see the PRD list ended without needing to see > >the INTRQ from the device? In particular, devices which lack INTRQ can > >be read and written via DMA, except that errors then appear as timeouts, > >recovered by reset? > > See the T13 Host Controller standard, especially the descriptions of > the controller's Start/Stop bit, the Active bit and the Interrupt > bit. > > Hale > > > > *** Hale Landis *** www.ata-atapi.com *** > >
