This message is from the T13 list server.
Dan
Now that I look at the text more closely, I think this needs an
agenda item.
Hale
The reason that it says "Shall not set the DRQ bit to one" instead
of shall not change the DRQ bit is because of the ATAPI devices I talked
about earlier.
I think we have found an inconsistency in ATA/ATAPI-7 between
5.14.5.5 and 5.14.5.7. 5.14.5.7 states that:
The ERR bit shall be set to one by the device:
1) when BSY or DRQ is set to one and an error occurs in the
executing command.
Please note the "or" in the clause. I have seen devices set the ERR bit
when DRQ=1. This is the section they quote.
Please also note 5.14.5.1: "After the host has written the Command register
the device shall have either the BSY bit set to one, or the DRQ bit set to
one, ..."
If this is truly the case, then if you are a device that sets DRQ=1 when the
command register is stored, you would have to be able to set ERR=1 when
BSY=0.
I think the text of the paragraph you are quoting is a little unclear. It
is in direct conflict with the list of reasons for setting BSY=1 item number
two. It is also in conflict with 5.15.5.5. I think that it is interesting
because in 5.15.5.5 it also says you can't set the BSY bit if you have set
the DRQ bit to indicate that the command has started.
------------------------------------------------
Curtis E. Stevens
20511 Lake Forest Drive #C-214D
Lake Forest, California 92630
Phone: 949-672-7933
Cell: 949-307-5050
E-Mail: [EMAIL PROTECTED]
My friends and I were on a beer run and noticed that the cases were
discounted 10%. Since it was a big party, we bought two cases. The cashier
multiplied two times 10% and gave us a 20% discount... and then he voted
-----Original Message-----
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Hale
Landis
Sent: Monday, November 15, 2004 10:04 PM
To: T13 List Server
Subject: Re: [t13] e04155r0 - DRQ=0 When ERR=1 Feature
This message is from the T13 list server.
Curtis Stevens wrote:
> This message is from the T13 list server.
> Hale
> I would like you to please looks at 5.14.5.5 in ATA/ATAPI-7 v1 also
> please look at 5.14.5.7. As you can see, the ERR bit can change when DRQ
or
> BSY is 1. This is normal PATA operation as I understand it. Further, I
> believe these sections make it clear that DRQ does not require BSY=1 to
> change.
Yes, the ERR bit may change when BSY=1 (in fact, that is the only time
the ERR bit should change from 0 to 1). Note that the ERR bit changes
from 1 to 0 on a number of conditions in section 5.14.x (such as a write
to the Command register).
In section "5.14.5.1 BSY (Busy)" the following text is found:
When BSY is cleared to zero, the host has control of the
Command Block registers, the device shall:
1) not set DRQ to one;
2) not change ERR bit;
3) not change the content of any other Command Block register;
4) set the SERV bit to one when ready to continue an overlapped
command that has been bus released.
5) clear the DSC bit to zero when an action that uses this bit
is completed.
Yes, when BSY=0 DRQ=1 the device may change the value of the ERR bit but
that would be dangerous because a host may not see that change (because
it is not common for hosts to read status while in the middle of reading
/writing the data register during PIO data transfers.
And yes, the PIO Data In command protocol does specify that DRQ chagnes
from 1 to 0 (without BSY=1) when the last word of the last DRQ data
block is tranferred by the host.
And yes, the PIO Data Out and PACKET command protocols allow a device to
change DRQ from 0 to 1 without BSY=1 but only immediately after the
command register has been written (and not at any other time).
I hope this helps.
Hale
--
++ Hale Landis ++ www.ata-atapi.com ++
