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Curtis Stevens wrote:
This message is from the T13 list server. Hale I would like you to please looks at 5.14.5.5 in ATA/ATAPI-7 v1 also please look at 5.14.5.7. As you can see, the ERR bit can change when DRQ or BSY is 1. This is normal PATA operation as I understand it. Further, I believe these sections make it clear that DRQ does not require BSY=1 to change.
Yes, the ERR bit may change when BSY=1 (in fact, that is the only time the ERR bit should change from 0 to 1). Note that the ERR bit changes from 1 to 0 on a number of conditions in section 5.14.x (such as a write to the Command register).
In section "5.14.5.1 BSY (Busy)" the following text is found:
When BSY is cleared to zero, the host has control of the Command Block registers, the device shall:
1) not set DRQ to one;
2) not change ERR bit;
3) not change the content of any other Command Block register;
4) set the SERV bit to one when ready to continue an overlapped command that has been bus released.
5) clear the DSC bit to zero when an action that uses this bit is completed.
Yes, when BSY=0 DRQ=1 the device may change the value of the ERR bit but that would be dangerous because a host may not see that change (because it is not common for hosts to read status while in the middle of reading /writing the data register during PIO data transfers.
And yes, the PIO Data In command protocol does specify that DRQ chagnes from 1 to 0 (without BSY=1) when the last word of the last DRQ data block is tranferred by the host.
And yes, the PIO Data Out and PACKET command protocols allow a device to change DRQ from 0 to 1 without BSY=1 but only immediately after the command register has been written (and not at any other time).
I hope this helps.
Hale
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++ Hale Landis ++ www.ata-atapi.com ++
