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I guess what would have to happen is in the case of the last sector of a read, if an error has occured the last sector would never be transferred. So rather than going to BSY = 0, DRQ = 1, ERR = 1 state for that last transfer it would do directly to BSY = 0, DRQ = 0, ERR = 1 and the host would have to terminate based on ERR being set. That would definately elimanate the window I am thinking about and since only a host that is aware of this feature would enable it, then it shouldn't be a problem for existing hardware. hmmm....Still scares me. gary > > From: Pat LaVarre <[EMAIL PROTECTED]> > Date: 2004/11/15 Mon PM 05:55:52 EST > To: <[EMAIL PROTECTED]> > Subject: Re: [t13] e04155r0 - DRQ=0 When ERR=1 Feature > > > Example: is it is virtually impossible to clear DRQ at exactly the > > same time that ERR is set. Hence there will always be some sort of > > overlap where the state is undefined (DRQ -> 0 whiles ERR -> 1). That > > is the window I am concerned about. > > Yes, it's difficult to avoid seeing a spurious b11 or b00 in the change > between b01 and b10: that's why Gray codes exist. But to avoid DRQ and > ERR appearing together, we should be asking the device to clear both or > either before clearing BSY. That's something device hardware - though > maybe not device firmware - actually can easily choose to do. > > Pat LaVarre > > P.S. How exactly ATA and ATAPI device hardware folk arrange for BSY DRQ > to cycle always thru b 00 10 11 01 11 10 00 and make b11 rare and never > spuriously produce a b00 in the middle, I've never entirely understood. > Any ASIC folk want to comment? Seems like double-latching to > synchronise clocks would open a b11 window wide ... > > gary laatsch [EMAIL PROTECTED]
