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Eschmann, Michael K wrote:
>This message is from the T13 list server.
Hale, you basically just said that everything in the areas of the spec that you listed must be followed, but failed to answer why we have inconsistencies in the areas that you just agreed to. One of the controversial issues surrounds two clauses
A: >> When BSY is cleared to zero, the host has control of the Command >> Block registers, the device shall: >> 1) not set DRQ to one; >> 2) not change ERR bit;
B: >> The ERR bit shall be set to one by the device: >> 1) when BSY or DRQ is set to one and an error occurs in the >> executing command.
A1 and A2 conflict with the ability of B1 from happening if BSY is clear, which is allowed by B. Are you saying that B1 is worded incorrectly (that pesky "or")?
OK... I can see that A2 would appear to conflict with B1. My suggestions:
1)remove the "or DRQ" from B1 - however, this will cause much hardware to not conform to the standard;
2) change A2 to say "not change [the] ERR bit unless DRQ is set to one" - this is the much safer change to make.
The problem here is that there is lots of device hardware that will, during command execution, set ERR=1 at the time the error is detected asynchronously to the interface activity. This type of device hardware may set ERR=1 while BSY=1 (clearly that is OK) and also while BSY=0 DRQ=1 (and that should not be a problem expect if it happens during the transfer of the last DRQ data block of a PIO Data In command - because some hosts may not see it - because tradition says the final status of a PIO Data In command is presented to the host when BSY=0 DRQ=1 status is set before the transfer of the last DRQ data block is is done by the host). Note that the ERR bit is "stickly" and will remain set to 1 until the next command or a reset is issued.
> So after all the text you put down you
appear to be concerned about the validity of BSY=0 DRQ=1 and ERR=1? Please help us focus here.
Does this help?
Hale
--
++ Hale Landis ++ www.ata-atapi.com ++
