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The following is a copy of section 3.1.2.6 from the definitions section of volume 2. >> 3.1.2.6 command completion: Command completion is the completion by the device of the action requested by the command or the termination of the command with an error, the placing of the appropriate error bits in the Error register, the placing of the appropriate status bits in the Status register, the clearing of both BSY and DRQ to zero, and Interrupt Pending. << It is very clear that both BSY and DRQ are to be cleared to zero before the host can determine that the command is complete and make any conclusions from the content of the rest of the Status register. I count 7 instances of the phrase "the host shall wait 400ns before reading the Status register" in the protocol section of volume 2. Any host that issues a command and then interprets the contents of the status register before 400ns has expired is basically asking for trouble (it is broken!) DRQ has only any real significance in PIO transfers (its use in determining the start of a DMA transfer is qualified with DMARQ). The HOST protocol sections of volume 2 make it very clear that once a transfer is initiated the Host shall complete the DRQ data block before looking at the status register. This gives the device time to set BSY/DRQ before the host has a look to see if the device is ready for the next block or it has completed or terminated the transfer. Again the Host state diagrams in the protocol section of volume 2 make it clear that ONLY if BOTH BSY and DRQ are cleared to zero has the command completed and only then does the error bit have any meaning (see 3.1.2.6). It should be remembered that during a PIO transfer the host is in charge of clocking the data in or out. Even if the device determines that there is an error and ignores data written to it or does not actively drive the bus on a read the Host SHALL complete the DRQ block and only then take any notice of the Status register. The host is free to read the Status register at any time but should not take any action unless the DRQ block is complete. I do not see how the standard can be any clearer! -----Original Message----- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Hale Landis Sent: Wednesday, 17 November, 2004 22:12 To: T13 List Server Subject: RE: [t13] PATA BSY DRQ ERR descriptions from ATA/ATAPI-7 This message is from the T13 list server. On Wed, 17 Nov 2004 14:47:16 -0800, Curtis Stevens wrote: >This message is from the T13 list server. >I have many things to say, but I have drawn my conclusions >and am saving them for F2F discussion at T13. That's unfortunate for some of us that don't attend meetings. >I believe that there is an inconsistency in >the standard, but I only want clarity, not new functionality. My proposal is... In section "5.14.5.1 BSY (Busy)" change the text "2) not change ERR bit;" to "2) not change the ERR bit unless DRQ is set to one;" >I do not know >if BSY=0 and DRQ=1 when the command register is stored is a useful item to >document at this point. I see no reason to change anything here. The case of a device going directly to status of BSY=0 DRQ=1 when the command register is written is covered by the following text also in section "5.14.4.1 BSY (Busy)": "NOTE - The BSY bit may be set to one and then cleared to zero so quickly, that host detection of the BSY bit being set to one is not certain." What more needs to be said? Hale *** Hale Landis *** www.ata-atapi.com ***
