-----Original Message-----
From: David Cary [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, June 13, 2001 1:37 PM
To: Protel EDA Forum
Cc: [EMAIL PROTECTED]
Subject: Re: [PEDA] SMT Land Pattern Design
[EMAIL PROTECTED] on 2001-05-30 01:03:23 PM
>>I was just using the IPC-SM-782 Land Pattern Calculator
>
>So was I, but I must be using it wrong because it never species the PLMT
>GRID. Were you looking up a part or designing a land pattern?
I was just looking up a part.
If the calculation for PLMT GRID is really as simple as Brendon Slade says
it
is, I don't know why the online calculator doesn't go ahead and calculate it
as
well.
Take maximum extent in the x direction (in mm), add 1 mm of clearance
between
components, multiply by 2 and round up to next larger integer.
Hm... today I'm double-checking my 6032 case size tantalum capactor.
If I use that algorithm with
Lmax = 3.4
Wmax = 1.8
With that simple algorithm, I expect to get a placement grid of 6X9, but IPC
gives PLMT GRID = 6X12.
I wonder how they got that ?
The reason I'm checking is that the libraries that came on the Protel CD
have 2
slightly different footprints for the 6032 package (with exactly the same
name
-- whoops.):
PCBfootprints.lib | 6032 : 3.05 x 2.29 mm pads, 6.10 center-to-center
DiscreteIPC.lib | 6032 : 2.60 x 2.20 mm pads, 5.0 mm center-to-center
http://search.ipc.org/sm782/ | Tantalum capacitors | TC6032:
2.60 x 2.20 mm pads, 5.0 mm center-to-center.
http://www.avxcorp.com/docs/masterpubs/smtc.pdf page 48:
reflow: 2.0 x 2.8 mm pads, 4.5 mm center-to-center.
wave solder: 2.0 x 1.6 mm pads, 4.5 mm center-to-center.
Unfortunately, the footprint in the DiscreteIPC.lib does not indicate anode
vs.
cathode (and tantalum capacitors *are* polarized).
--
David Cary
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