david, you could implement a pretty quick and dirty SRC with a pair of CICs
CICs are quite cheap on that sort of processor... rather than a polyphase FIR .... (but I gather that is not what is chewing up the processor) (something must be "not right") go 8000 >> 120000 (upsample by 15) then to 7500 (downsample by 16) you might need a 1:2 upsample and downsample 2:1 at each end to get away from the CIC droop but, the SNR and aliasing requirements are very low a continuously variable FARROW filter is also a good option, just needs a few parabolic terms computed each sample. essentially you give the equation the sample rate ratio (arbritary), good for pulling to fixed rate stuff. :-) g On 8/02/2017 8:14 PM, wully wrote: > Hi David > > I have further analyzed the api-Problem with to much timelapse for the > freedv_rx(): > > When you use 8000S/s as input, your downsampling and filtering requires > a steep filter for 8000->7500. > In my code, which directely uses 7500, I come in with 96000S/s and can > easily downsam ------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, SlashDot.org! http://sdm.link/slashdot _______________________________________________ Freetel-codec2 mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/freetel-codec2
