On Oct 13, 2008, at 10:19 PM, Paul wrote:
> Apparently the G4 firmware update stopped allowing the use of CL2 RAM > that couldn't also run at CL3: > http://chrislawson.net/writing/techref/010503.shtml "This is a lot like what happened with the RAM modules. As best anyone can tell (and nobody really knows for sure), Apple's firmware update dropped the RAM timing back from 2-2-2 (the fastest speed) to 3-2-2 (only very slightly slower) for the sake of stability (to get rid of that vibration in the unbalanced wheel, if you will). RAM modules that didn't have information about how to run in 3-2-2 mode, a mode they should be completely backwards-compatible with according to the JEDEC standards, in their EPROM chips failed when the firmware update was applied." Apple-installed RAM was 3-3-3. Every bit of it which I have personally examined, that is, which is a lot. It was after-sale RAM which did not match Apple's original RAM spec of 3-3-3. Some such RAM was 3-2-2, but not a lot, in my experience. Most, in my experience, was also 3-3-3. 3-3-3 and 3-2-2 can coexist, at least on my DAs and QSes. Perhaps 100 MHz bus machines have this problem more often than 133 MHz bus machines, although every 100 MHz bus machine I own accepts 3-3-3 and 3-2-2 equally well. Since I mainly stock 512 MB sticks, until my recent sell-off of such RAM sticks, I haven't seen a lot of 256 MB CL2 sticks. All my PPC machines, regardless of bus speed, are at the highest firmware level. One problem which Apple may have exacerbated is RAM modules which SPD had the codes for both 3-3-3 and 3-2-2, for which I believe Apple's POST code was confused by the presence of two specifications. OWC, which was turning out such sticks, got caught between JEDEC's specs (to which its products adhered) and Apple's interpretation of said specs (through which its POST code obviously became confused), with the result that the sticks were reprogrammed by OWC to specify one or the other, but not both, even though Apple's POST code should have been happy. I cannot imagine a RAM stick which runs correctly at CL2 (two clock cycles of CAS latency), but which fails with the looser timing of CL3 (three clock cycles of CAS latency). --~--~---------~--~----~------------~-------~--~----~ You received this message because you are subscribed Low End Mac's G3-5 List, a group for those using G3, G4, and G5 desktop Macs - with a particular focus on Power Macs. The list FAQ is at http://lowendmac.com/lists/g-list.shtml and our netiquette guide is at http://www.lowendmac.com/lists/netiquette.shtml To post to this group, send email to [email protected] To unsubscribe from this group, send email to [EMAIL PROTECTED] For more options, visit this group at http://groups.google.com/group/g3-5-list?hl=en Low End Mac RSS feed at feed://lowendmac.com/feed.xml -~----------~----~----~----~------~----~------~--~---
