[Bug tree-optimization/122635] RISC-V: -mrvv-vector-bits=zvl introducing unoptimal vsetivli zero,0 and insns depending on AVL nops

[gkm at rivosinc dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122635

--- Comment #12 from Greg McGary <gkm at rivosinc dot com> ---
(In reply to Andrew Pinski from comment #10)
> You might need to replace it with a GIMPLE_NOP (look for other places that
> do gimple_build_nop).

Understood. That works. Next: the removed MASK_LEN_LOAD is the head of a
def-use chain that now needs to be pruned. What is the best API for that?