[Bug tree-optimization/122635] RISC-V: -mrvv-vector-bits=zvl introducing unoptimal vsetivli zero,0 and insns depending on AVL nops

[law at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122635

--- Comment #15 from Jeffrey A. Law <law at gcc dot gnu.org> ---
I'd tend to go towards option #1 -- it fixes things at the root cause.  I'm not
a fan of adding more passes and option #3 seems like it's just papering over
the problem.

Though as Robin noted, it can be tackled in DSE as well.  We ought to be able
to elide any zero length stores.  We typically have a DCE pass after DSE to
clean up statements that were feeding the dead store.