[Bug tree-optimization/122635] RISC-V: -mrvv-vector-bits=zvl introducing unoptimal vsetivli zero,0 and insns depending on AVL nops

[law at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122635

--- Comment #13 from Jeffrey A. Law <law at gcc dot gnu.org> ---
I would kind of expect that DCE would clean this up if you've neutered the main
operation.  I'd look at the next DCE dump and see if everything you want
magically disappeared.