[Bug target/128162] [17 Regression] wrong code at -O2: vwmacc.vx whose source is the upper half of the accumulator raises SIGILL

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=128162

--- Comment #5 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <pa...@gcc.gnu.org>:

https://gcc.gnu.org/g:62e0fe6ce26047129244e7a1c5f0fb829f67a309

commit r17-5716-g62e0fe6ce26047129244e7a1c5f0fb829f67a309
Author: Pan Li <pan2...@intel.com>
Date:   Wed Oct 28 10:36:35 2026 +0800

    RISC-V: Disable RVV register overlap for vfw{macc,msac}.vv [PR
target/128162]

    Revert the register overlap of the widening multiply-add insn
    vfw{macc,msac}.vv and the related test cases.

    The insn reads the vd as the accumulator with EEW = 2 * SEW, while
    the vs1 and vs2 are read with EEW = SEW.  The section 5.2 of the
    vector spec reserves any encoding in which one vector register
    supplies source operands with two or more different EEWs.  Thus,
    the vs1 and vs2 must not overlap the vd register group, even in the
    highest-numbered part.  For example, below asm dump is reserved as
    the v3 is read with both the EEW = 32 and the EEW = 16.

      vfwmacc.vv v2,v3,v4   # LMUL = 1, SEW = 16

    This reverts commit(s):
      dafa6930eb5 RISC-V: Allow RVV register overlap for vfw{macc,msac}.vv
      cfb973b3441 RISC-V: Add test cases for vfwmacc.vv reg overlap
      4c8452662e9 RISC-V: Add test cases for vfwmsac.vv reg overlap
      9c73440b6f8 RISC-V: Add more test cases for vfw{macc,msac}.vv

            PR target/128162

    gcc/ChangeLog:

            * config/riscv/vector.md: Revert Wvr constraint to the
            early clobber vr.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f16-m1.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f16-m2.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f16-m4.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f16-mf2.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f16-mf4.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f32-m1.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f32-m2.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f32-m4.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f32-mf2.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-m1.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-m2.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-m4.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-mf2.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-mf4.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-m1.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-m2.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-m4.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-mf2.c:
Removed.
            * gcc.target/riscv/rvv/base/pr112431-61.c: Removed.
            * gcc.target/riscv/rvv/base/pr112431-62.c: Removed.

    Signed-off-by: Pan Li <pan2...@intel.com>