[Bug target/128162] [17 Regression] wrong code at -O2: vwmacc.vx whose source is the upper half of the accumulator raises SIGILL

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=128162

--- Comment #7 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <pa...@gcc.gnu.org>:

https://gcc.gnu.org/g:a890119da9c92bae6d87b7fff77a60f3b33835fb

commit r17-5718-ga890119da9c92bae6d87b7fff77a60f3b33835fb
Author: Pan Li <pan2...@intel.com>
Date:   Wed Oct 28 10:36:53 2026 +0800

    RISC-V: Disable RVV register overlap for vwmaccus.vx [PR target/128162]

    Revert the register overlap of the widening multiply-add insn
    vwmaccus.vx and the related test cases.

    The insn reads the vd as the accumulator with EEW = 2 * SEW, while
    the vs1 and vs2 are read with EEW = SEW.  The section 5.2 of the
    vector spec reserves any encoding in which one vector register
    supplies source operands with two or more different EEWs.  Thus,
    the vs1 and vs2 must not overlap the vd register group, even in the
    highest-numbered part.  For example, below asm dump is reserved as
    the v3 is read with both the EEW = 32 and the EEW = 16.

      vwmaccus.vx v2,a0,v3   # LMUL = 1, SEW = 16

    This reverts commit(s):
      b933df353a1 RISC-V: Allow RVV register overlap for vwmaccus.vx
      e485ab3fc8b RISC-V: Add test cases for vwmaccus.vx reg overlap
      5983249d806 RISC-V: Add more test cases for vwmaccus.vx

            PR target/128162

    gcc/ChangeLog:

            * config/riscv/vector.md: Revert Wvr constraint to the
            early clobber vr.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-m1.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-m2.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-m4.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-mf2.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-mf4.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i32-m1.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i32-m2.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i32-m4.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i32-mf2.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-m1.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-m2.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-m4.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-mf2.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-mf4.c:
Removed.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-mf8.c:
Removed.
            * gcc.target/riscv/rvv/base/pr112431-57.c: Removed.
            * gcc.target/riscv/rvv/base/pr112431-58.c: Removed.
            * gcc.target/riscv/rvv/base/pr112431-37.c: Add xfail back.

    Signed-off-by: Pan Li <pan2...@intel.com>