https://gcc.gnu.org/g:aafb3a221136ffa4aff2995d241b9ba621540478
commit aafb3a221136ffa4aff2995d241b9ba621540478 Author: Michael Meissner <[email protected]> Date: Mon Oct 20 19:37:56 2025 -0400 Use power7 CPU option for power7 support instead of -mpopcntd See https://gcc.gnu.org/pipermail/gcc-patches/2025-September/695920.html for more detail about the motavation for this set of patches. This is the tenth patch out of ten that cleans up most of the power7 support not to use -mpopcntd to indicate we are using power7. I believe the -mpopcntd option should be deprecated for GCC 17, but because it is a documented switch, I have left it in these sets of patches. I have made -mpopcntd only restrict uses of the actual popcntd instruction. I have bootstraped and ran the regression tests for these patches on both little endian and big endian Power servers. Can I check these patches into the trunk? 2025-10-20 Michael Meissner <[email protected]> gcc/ * config/rs6000/dfp.h (cmp<mode>_internal1): Use power7 CPU option support instead of -mpopcntd, except for population count instructions. * config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Likewise. * config/rs6000/rs6000-string.cc (expand_block_compare_gpr): Likewise. * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Likewise. (rs6000_option_override_internal): Likewise. * config/rs6000/rs6000.h (TARGET_LDBRX): Likewise. (TARGET_FCFID): Likewise. (TARGET_LFIWZX): Likewise. (TARGET_FCFIDS): Likewise. (TARGET_FCFIDU): Likewise. (TARGET_FCFIDUS): Likewise. (TARGET_FCTIDUZ): Likewise. (TARGET_FCTIWUZ): Likewise. (TARGET_EXTRA_BUILTINS): Likewise. (TARGET_POWER7): New macro. * config/rs6000/rs6000.md (isa attribute): Use power7 CPU option support instead of -mpopcntd, except for population count instructions. (lrint<mode>s): Likewise. (lrint<mode>si_di): Likewise. (cmpmemsi): Likewise. (bpermd_<mode>): Likewise. (addg6s): Likewise. (cdtbcd): Likewise. (cbcdtd): Likewise. (div<div_extend>_<mode>): Likewise. Diff: --- gcc/config/rs6000/dfp.md | 2 +- gcc/config/rs6000/rs6000-builtin.cc | 4 ++-- gcc/config/rs6000/rs6000-string.cc | 4 ++-- gcc/config/rs6000/rs6000.cc | 6 +++--- gcc/config/rs6000/rs6000.h | 20 +++++++++++--------- gcc/config/rs6000/rs6000.md | 18 +++++++++--------- 6 files changed, 28 insertions(+), 26 deletions(-) diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md index 825e7c54e73e..4c6306c3c607 100644 --- a/gcc/config/rs6000/dfp.md +++ b/gcc/config/rs6000/dfp.md @@ -214,7 +214,7 @@ (define_insn "floatdidd2" [(set (match_operand:DD 0 "gpc_reg_operand" "=d") (float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))] - "TARGET_DFP && TARGET_POPCNTD" + "TARGET_DFP && TARGET_POWER7" "dcffix %0,%1" [(set_attr "type" "dfp")]) diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index bc1580f051b0..dfbb7d02157b 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -161,9 +161,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode) case ENB_P6_64: return TARGET_CMPB && TARGET_POWERPC64; case ENB_P7: - return TARGET_POPCNTD; + return TARGET_POWER7; case ENB_P7_64: - return TARGET_POPCNTD && TARGET_POWERPC64; + return TARGET_POWER7 && TARGET_POWERPC64; case ENB_P8: return TARGET_POWER8; case ENB_P8V: diff --git a/gcc/config/rs6000/rs6000-string.cc b/gcc/config/rs6000/rs6000-string.cc index 561297b0ba46..4ba7ef6bdb42 100644 --- a/gcc/config/rs6000/rs6000-string.cc +++ b/gcc/config/rs6000/rs6000-string.cc @@ -1948,8 +1948,8 @@ expand_block_compare_gpr(unsigned HOST_WIDE_INT bytes, unsigned int base_align, bool expand_block_compare (rtx operands[]) { - /* TARGET_POPCNTD is already guarded at expand cmpmemsi. */ - gcc_assert (TARGET_POPCNTD); + /* TARGET_POWER7 is already guarded at expand cmpmemsi. */ + gcc_assert (TARGET_POWER7); /* For P8, this case is complicated to handle because the subtract with carry instructions do not generate the 64-bit carry and so diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 4e0b7ef7136c..44bcf9664121 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -1925,7 +1925,7 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode) if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD) return 1; - if (TARGET_POPCNTD && mode == SImode) + if (TARGET_POWER7 && mode == SImode) return 1; if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode)) @@ -3923,7 +3923,7 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks); else if (TARGET_VSX) rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks); - else if (TARGET_POPCNTD) + else if (TARGET_POWER7) rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks); else if (TARGET_DFP) rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks); @@ -4136,7 +4136,7 @@ rs6000_option_override_internal (bool global_init_p) else if (TARGET_LONG_DOUBLE_128) { if (global_options.x_rs6000_ieeequad - && (!TARGET_POPCNTD || !TARGET_VSX)) + && (!TARGET_POWER7 || !TARGET_POPCNTD || !TARGET_VSX)) error ("%qs requires full ISA 2.06 support", "-mabi=ieeelongdouble"); if (rs6000_ieeequad != TARGET_IEEEQUAD_DEFAULT) diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 1bd2ce53cc7b..643aa2449318 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -443,7 +443,7 @@ extern int rs6000_vector_align[]; #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64) #define TARGET_IEEEQUAD rs6000_ieeequad #define TARGET_ALTIVEC_ABI rs6000_altivec_abi -#define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL) +#define TARGET_LDBRX (TARGET_POWER7 || rs6000_cpu == PROCESSOR_CELL) /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only. Enable 32-bit fcfid's on any of the switches for newer ISA machines. */ @@ -451,17 +451,17 @@ extern int rs6000_vector_align[]; || TARGET_PPC_GPOPT /* 970/power4 */ \ || TARGET_POPCNTB /* ISA 2.02 */ \ || TARGET_CMPB /* ISA 2.05 */ \ - || TARGET_POPCNTD) /* ISA 2.06 */ + || TARGET_POWER7) /* ISA 2.06 */ #define TARGET_FCTIDZ TARGET_FCFID #define TARGET_STFIWX TARGET_PPC_GFXOPT #define TARGET_LFIWAX TARGET_CMPB -#define TARGET_LFIWZX TARGET_POPCNTD -#define TARGET_FCFIDS TARGET_POPCNTD -#define TARGET_FCFIDU TARGET_POPCNTD -#define TARGET_FCFIDUS TARGET_POPCNTD -#define TARGET_FCTIDUZ TARGET_POPCNTD -#define TARGET_FCTIWUZ TARGET_POPCNTD +#define TARGET_LFIWZX TARGET_POWER7 +#define TARGET_FCFIDS TARGET_POWER7 +#define TARGET_FCFIDU TARGET_POWER7 +#define TARGET_FCFIDUS TARGET_POWER7 +#define TARGET_FCTIDUZ TARGET_POWER7 +#define TARGET_FCTIWUZ TARGET_POWER7 /* Only powerpc64 and powerpc476 support fctid. */ #define TARGET_FCTID (TARGET_POWERPC64 || rs6000_cpu == PROCESSOR_PPC476) #define TARGET_CTZ TARGET_MODULO @@ -528,7 +528,7 @@ extern int rs6000_vector_align[]; || TARGET_PPC_GPOPT /* 970/power4 */ \ || TARGET_POPCNTB /* ISA 2.02 */ \ || TARGET_CMPB /* ISA 2.05 */ \ - || TARGET_POPCNTD /* ISA 2.06 */ \ + || TARGET_POWER7 /* ISA 2.06 */ \ || TARGET_ALTIVEC \ || TARGET_VSX \ || TARGET_HARD_FLOAT) @@ -558,6 +558,8 @@ extern int rs6000_vector_align[]; /* ISA bits that are set via -mcpu=<xxx>, but that do not have an associated switch with the option. */ +#define TARGET_POWER7 \ + ((rs6000_cpu_option_flags & CPU_OPTION_POWER7_MASK) != 0) #define TARGET_POWER8 \ ((rs6000_cpu_option_flags & CPU_OPTION_POWER8_MASK) != 0) #define TARGET_POWER9 \ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index d0fad09abd10..edb624fcc9e7 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -387,7 +387,7 @@ (const_int 1) (and (eq_attr "isa" "p7") - (match_test "TARGET_POPCNTD")) + (match_test "TARGET_POWER7")) (const_int 1) (and (eq_attr "isa" "p7v") @@ -6801,7 +6801,7 @@ [(set (match_operand:SI 0 "gpc_reg_operand" "=d") (unspec:SI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")] UNSPEC_FCTIW))] - "TARGET_HARD_FLOAT && TARGET_POPCNTD" + "TARGET_HARD_FLOAT && TARGET_POWER7" "fctiw %0,%1" [(set_attr "type" "fp")]) @@ -6809,7 +6809,7 @@ [(set (match_operand:DI 0 "gpc_reg_operand" "=d") (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")] UNSPEC_FCTIW))] - "TARGET_HARD_FLOAT && !TARGET_POPCNTD" + "TARGET_HARD_FLOAT && !TARGET_POWER7" "fctiw %0,%1" [(set_attr "type" "fp")]) @@ -10173,7 +10173,7 @@ (match_operand:BLK 2))) (use (match_operand:SI 3)) (use (match_operand:SI 4))])] - "TARGET_POPCNTD" + "TARGET_POWER7" { if (optimize_insn_for_size_p ()) FAIL; @@ -14440,7 +14440,7 @@ [(set (match_operand:P 0 "gpc_reg_operand" "=r") (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r") (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))] - "TARGET_POPCNTD" + "TARGET_POWER7" "bpermd %0,%1,%2" [(set_attr "type" "popcnt")]) @@ -14818,7 +14818,7 @@ (unspec:SI [(match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "register_operand" "r")] UNSPEC_ADDG6S))] - "TARGET_POPCNTD" + "TARGET_POWER7" "addg6s %0,%1,%2" [(set_attr "type" "integer")]) @@ -14826,7 +14826,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_CDTBCD))] - "TARGET_POPCNTD" + "TARGET_POWER7" "cdtbcd %0,%1" [(set_attr "type" "integer")]) @@ -14834,7 +14834,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_CBCDTD))] - "TARGET_POPCNTD" + "TARGET_POWER7" "cbcdtd %0,%1" [(set_attr "type" "integer")]) @@ -14849,7 +14849,7 @@ (unspec:GPR [(match_operand:GPR 1 "register_operand" "r") (match_operand:GPR 2 "register_operand" "r")] UNSPEC_DIV_EXTEND))] - "TARGET_POPCNTD" + "TARGET_POWER7" "div<wd><div_extend> %0,%1,%2" [(set_attr "type" "div") (set_attr "size" "<bits>")])
