https://gcc.gnu.org/g:001b3a711d88850d046a59ca8aa38e845cb6747c
commit r17-371-g001b3a711d88850d046a59ca8aa38e845cb6747c Author: Pan Li <[email protected]> Date: Tue May 5 13:44:46 2026 +0800 RISC-V: Combine vec_duplicate + vmsgt.vv to vmsgt.vx on GR2VR cost This patch would like to combine the vec_duplicate + vmsgt.vv to the vmsgt.vx. From example as below code. The related pattern will depend on the cost of vec_duplicate from GR2VR. Then the late-combine will take action if the cost of GR2VR is zero, and reject the combination if the GR2VR cost is greater than zero. Assume we have asm code like below, GR2VR cost is 0. Before this patch: 11 beq a3,zero,.L8 12 vsetvli a5,zero,e32,m1,ta,ma 13 vmv.v.x v2,a2 ... 16 .L3: 17 vsetvli a5,a3,e32,m1,ta,ma ... 22 vmsgt.vv v1,v2,v3 ... 25 bne a3,zero,.L3 After this patch: 11 beq a3,zero,.L8 ... 14 .L3: 15 vsetvli a5,a3,e32,m1,ta,ma ... 20 vmsgt.vx v1,a2,v3 ... 23 bne a3,zero,.L3 gcc/ChangeLog: * config/riscv/predicates.md: Add lt to swapped operator. * config/riscv/riscv-v.cc (get_swapped_cmp_rtx_code): Handle the rtl as well. Signed-off-by: Pan Li <[email protected]> Diff: --- gcc/config/riscv/predicates.md | 2 +- gcc/config/riscv/riscv-v.cc | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 4116674601ce..47e634ad87f1 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -612,7 +612,7 @@ (match_code "eq,ne,le,leu,gt,gtu,lt,ltu")) (define_predicate "comparison_swappable_operator" - (match_code "gtu,gt,geu,ge,ltu")) + (match_code "gtu,gt,geu,ge,ltu,lt")) (define_predicate "ge_operator" (match_code "ge,geu")) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 2103764da06e..eabc792f8b7d 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -6075,6 +6075,8 @@ get_swapped_cmp_rtx_code (rtx_code code) return LE; case LTU: return GTU; + case LT: + return GT; default: gcc_unreachable (); }
