https://gcc.gnu.org/g:b1987874feead5e98f1ea005bd1ce5ff515eda7a
commit r17-372-gb1987874feead5e98f1ea005bd1ce5ff515eda7a Author: Pan Li <[email protected]> Date: Tue May 5 13:47:32 2026 +0800 RISC-V: Add test for vec_duplicate + vmsgt.vv combine with GR2VR cost 0, 1 and 15 Add asm dump check and run test for vec_duplicate + vmsgt.vv combine to vmsgt.vx, with the GR2VR cost is 0, 2 and 15. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check for vmsgt.vx. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add test helper macros. * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test data for run test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i32.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i64.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i8.c: New test. Signed-off-by: Pan Li <[email protected]> Diff: --- .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h | 1 + .../riscv/rvv/autovec/vx_vf/vx_binary_data.h | 136 +++++++++++++++++++++ .../riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i16.c | 15 +++ .../riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i32.c | 15 +++ .../riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i64.c | 15 +++ .../riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i8.c | 15 +++ 18 files changed, 209 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c index 683e7cebb286..b27bb338ee27 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c @@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmslt.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmsle.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmsgt.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c index 07dcc2ec7e5c..bc9b80f67cd9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c @@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmslt.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmsle.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmsgt.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c index b30fe640d213..9b8de9cfea1f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c @@ -34,3 +34,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmslt.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmsle.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmsgt.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c index 01b426afbfbb..2e6ec2088586 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c @@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmslt.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmsle.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmsgt.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c index 532e1884aea5..2d8263e04877 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c @@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmsne.vx} } } */ /* { dg-final { scan-assembler-not {vmslt.vx} } } */ /* { dg-final { scan-assembler-not {vmsle.vx} } } */ +/* { dg-final { scan-assembler-not {vmsgt.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c index 5ed2711c0320..bacf86c296f8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c @@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmsne.vx} } } */ /* { dg-final { scan-assembler-not {vmslt.vx} } } */ /* { dg-final { scan-assembler-not {vmsle.vx} } } */ +/* { dg-final { scan-assembler-not {vmsgt.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c index b494695098e6..e32719036d0e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c @@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmsne.vx} } } */ /* { dg-final { scan-assembler-not {vmslt.vx} } } */ /* { dg-final { scan-assembler-not {vmsle.vx} } } */ +/* { dg-final { scan-assembler-not {vmsgt.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c index 8fdee21f9316..aee6563b07b6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c @@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmsne.vx} } } */ /* { dg-final { scan-assembler-not {vmslt.vx} } } */ /* { dg-final { scan-assembler-not {vmsle.vx} } } */ +/* { dg-final { scan-assembler-not {vmsgt.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c index 841b88e4c2cd..2371d3fe250f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c @@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmsne.vx} } } */ /* { dg-final { scan-assembler-not {vmslt.vx} } } */ /* { dg-final { scan-assembler-not {vmsle.vx} } } */ +/* { dg-final { scan-assembler-not {vmsgt.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c index e80fdcc73576..4b343f66aece 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c @@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmslt.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ /* { dg-final { scan-assembler-not {vmsle.vx} } } */ +/* { dg-final { scan-assembler-not {vmsgt.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c index 548a3218e7f9..5b8b853c3207 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c @@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmsne.vx} } } */ /* { dg-final { scan-assembler-not {vmslt.vx} } } */ /* { dg-final { scan-assembler-not {vmsle.vx} } } */ +/* { dg-final { scan-assembler-not {vmsgt.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c index eb10722f2d2e..407261aad743 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c @@ -31,3 +31,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmsne.vx} } } */ /* { dg-final { scan-assembler-not {vmslt.vx} } } */ /* { dg-final { scan-assembler-not {vmsle.vx} } } */ +/* { dg-final { scan-assembler-not {vmsgt.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h index ff6b7f6542db..2291d9e9601c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h @@ -406,6 +406,7 @@ DEF_AVG_CEIL(int32_t, int64_t) DEF_VX_BINARY_CASE_0_WRAP(T, !=, ne) \ DEF_VX_BINARY_CASE_0_WRAP(T, <, lt) \ DEF_VX_BINARY_CASE_0_WRAP(T, <=, le) \ + DEF_VX_BINARY_CASE_0_WRAP(T, >, gt) \ DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_0_WARP(T), max) \ DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_1_WARP(T), max) \ DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_0_WARP(T), min) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h index 952c8b49ecd2..3cccd65b7498 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h @@ -7110,4 +7110,140 @@ uint64_t TEST_BINARY_DATA(uint64_t, gtu)[][3][N] = }, }; +int8_t TEST_BINARY_DATA(int8_t, gt)[][3][N] = +{ + { + { 127 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 127, 127, 127, 127, + -128, -128, -128, -128, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { -1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -2, -2, -2, -2, + -128, -128, -128, -128, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, gt)[][3][N] = +{ + { + { 32767 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 32767, 32767, 32767, 32767, + -32768, -32768, -32768, -32768, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { -1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -2, -2, -2, -2, + -32768, -32768, -32768, -32768, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, gt)[][3][N] = +{ + { + { 2147483647 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483648, -2147483648, -2147483648, -2147483648, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { -1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -2, -2, -2, -2, + -2147483648, -2147483648, -2147483648, -2147483648, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, gt)[][3][N] = +{ + { + { 9223372036854775807ll }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { -1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -2, -2, -2, -2, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, +}; + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i16.c new file mode 100644 index 000000000000..0c5c8bbe63d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME gt + +DEF_VX_BINARY_CASE_0_WRAP(T, >, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i32.c new file mode 100644 index 000000000000..239f029675ba --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME gt + +DEF_VX_BINARY_CASE_0_WRAP(T, >, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i64.c new file mode 100644 index 000000000000..fbc59bf6e8c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME gt + +DEF_VX_BINARY_CASE_0_WRAP(T, >, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i8.c new file mode 100644 index 000000000000..1fe1dbeaf29e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME gt + +DEF_VX_BINARY_CASE_0_WRAP(T, >, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h"
