https://gcc.gnu.org/g:a5e5f1f19e545f92e962cd62cef3c79825e8eecf
commit r17-972-ga5e5f1f19e545f92e962cd62cef3c79825e8eecf Author: Artemiy Volkov <[email protected]> Date: Fri Jan 9 17:50:22 2026 +0000 aarch64: add zeroing forms for predicated SVE bit reversal operations SVE2.2 (or in streaming mode, SME2.2) adds support for zeroing predication for the following SVE bit reversal instructions: - REVB, REVH, REVW (Reverse bytes / halfwords / words within elements (predicated)) - REVD (Reverse 64-bit doublewords in elements (predicated)) (SVE2 only) The first three are covered by the SVE_INT_UNARY code iterator, and REVD, being SVE2-only, has a standalone pattern in aarch64-sve2.md. This patch adds an alternative for the zeroing-predication forms of the original instructions. The pattern for REVD also required changes to the predicate for operand 3 to accept constant zero RTX whenever SVE2.2 is enabled. Additionally, use the /z form of the REVD instruction for PRED_X predication to save a data dependency. The tests that have been added are based on the original SVE/SVE2 tests for corresponding instructions, but all have a "_z" suffix in their name since they only test codegen for the "_z" variants of the corresponding intrinsics. gcc/ChangeLog: * config/aarch64/aarch64-sve.md (@cond_<optab><mode>): New alternative for zeroing predication. Add `arch` attribute to every alternative. * config/aarch64/aarch64-sve2.md (@aarch64_pred_<optab><mode>): Use zeroing predication variant for PRED_X. (@cond_<optab><mode>): Accept constant zero as operand 3. New alternative for zeroing predication. Add `arch` attribute to every alternative. * config/aarch64/predicates.md (aarch64_simd_reg_or_direct_zero): New predicate. gcc/testsuite/ChangeLog: * gcc.target/aarch64/sve2/acle/asm/revb_s16_z.c: New test. * gcc.target/aarch64/sve2/acle/asm/revb_s32_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/revb_s64_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/revb_u16_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/revb_u32_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/revb_u64_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/revd_bf16_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/revd_f16_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/revd_f32_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/revd_f64_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/revd_s16_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/revd_s32_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/revd_s64_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/revd_s8_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/revd_u16_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/revd_u32_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/revd_u64_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/revd_u8_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/revh_s32_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/revh_s64_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/revh_u32_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/revh_u64_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/revw_s64_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/revw_u64_z.c: Likewise. Diff: --- gcc/config/aarch64/aarch64-sve.md | 9 ++++--- gcc/config/aarch64/aarch64-sve2.md | 12 +++++---- gcc/config/aarch64/predicates.md | 9 +++++++ .../gcc.target/aarch64/sve2/acle/asm/revb_s16_z.c | 30 ++++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/revb_s32_z.c | 28 ++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/revb_s64_z.c | 28 ++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/revb_u16_z.c | 28 ++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/revb_u32_z.c | 28 ++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/revb_u64_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/revd_bf16_z.c | 28 ++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/revd_f16_z.c | 28 ++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/revd_f32_z.c | 28 ++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/revd_f64_z.c | 28 ++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/revd_s16_z.c | 28 ++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/revd_s32_z.c | 28 ++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/revd_s64_z.c | 28 ++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/revd_s8_z.c | 28 ++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/revd_u16_z.c | 28 ++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/revd_u32_z.c | 28 ++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/revd_u64_z.c | 28 ++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/revd_u8_z.c | 28 ++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/revh_s32_z.c | 30 ++++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/revh_s64_z.c | 28 ++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/revh_u32_z.c | 28 ++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/revh_u64_z.c | 30 ++++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/revw_s64_z.c | 28 ++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/revw_u64_z.c | 29 +++++++++++++++++++++ 27 files changed, 701 insertions(+), 9 deletions(-) diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 1bc0e7136cbf..8e4fc05e63fa 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -3590,10 +3590,11 @@ (match_operand:SVE_FULL_I 3 "aarch64_simd_reg_or_zero")] UNSPEC_SEL))] "TARGET_SVE && <elem_bits> >= <min_elem_bits>" - {@ [ cons: =0 , 1 , 2 , 3 ; attrs: movprfx ] - [ w , Upl , w , 0 ; * ] <sve_int_op>\t%0.<Vetype>, %1/m, %2.<Vetype> - [ ?&w , Upl , w , Dz ; yes ] movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;<sve_int_op>\t%0.<Vetype>, %1/m, %2.<Vetype> - [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %3\;<sve_int_op>\t%0.<Vetype>, %1/m, %2.<Vetype> + {@ [ cons: =0 , 1 , 2 , 3 ; attrs: movprfx, arch ] + [ w , Upl , w , 0 ; * , * ] <sve_int_op>\t%0.<Vetype>, %1/m, %2.<Vetype> + [ w , Upl , w , Dz ; * , sve2p2_or_sme2p2 ] <sve_int_op>\t%0.<Vetype>, %1/z, %2.<Vetype> + [ ?&w , Upl , w , Dz ; yes , * ] movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;<sve_int_op>\t%0.<Vetype>, %1/m, %2.<Vetype> + [ ?&w , Upl , w , w ; yes , * ] movprfx\t%0, %3\;<sve_int_op>\t%0.<Vetype>, %1/m, %2.<Vetype> } [(set_attr "sve_type" "sve_int_general")] ) diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md index d7031b522be4..2045b09e05b9 100644 --- a/gcc/config/aarch64/aarch64-sve2.md +++ b/gcc/config/aarch64/aarch64-sve2.md @@ -4130,8 +4130,9 @@ UNSPEC_REVD_ONLY)] UNSPEC_PRED_X))] "TARGET_SVE2p1_OR_SME" - {@ [ cons: =0 , 1 , 2 ] - [ w , Upl , 0 ] revd\t%0.q, %1/m, %2.q + {@ [ cons: =0 , 1 , 2 ; attrs: arch ] + [ w , Upl , 0 ; * ] revd\t%0.q, %1/m, %2.q + [ w , Upl , w ; sve2p2_or_sme2p2 ] revd\t%0.q, %1/z, %2.q } [(set_attr "sve_type" "sve_int_general")] ) @@ -4143,11 +4144,12 @@ (unspec:SVE_FULL [(match_operand:SVE_FULL 2 "register_operand")] UNSPEC_REVD_ONLY) - (match_operand:SVE_FULL 3 "register_operand")] + (match_operand:SVE_FULL 3 "aarch64_simd_reg_or_direct_zero")] UNSPEC_SEL))] "TARGET_SVE2p1_OR_SME" - {@ [ cons: =0 , 1 , 2 , 3 ] - [ w , Upl , w , 0 ] revd\t%0.q, %1/m, %2.q + {@ [ cons: =0 , 1 , 2 , 3 ; attrs: arch ] + [ w , Upl , w , 0 ; * ] revd\t%0.q, %1/m, %2.q + [ w , Upl , w , Dz ; sve2p2_or_sme2p2 ] revd\t%0.q, %1/z, %2.q } [(set_attr "sve_type" "sve_int_general")] ) diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index d64f3172affe..f02486c2d9a3 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -645,6 +645,15 @@ (match_test "op == const0_rtx") (match_operand 0 "aarch64_simd_or_scalar_imm_zero")))) +;; Same as above, but a zero const_vector is only allowed when a +;; corresponding single-insn (i.e. not involving MOVPRFX) alternative is +;; enabled. Used for zeroing predication forms of some SVE2.2 +;; instructions. +(define_predicate "aarch64_simd_reg_or_direct_zero" + (ior (and (match_test "TARGET_SVE2p2_OR_SME2p2") + (match_operand 0 "aarch64_simd_reg_or_zero")) + (match_operand 0 "register_operand"))) + (define_predicate "aarch64_simd_reg_or_minus_one" (ior (match_operand 0 "register_operand") (match_operand 0 "aarch64_simd_imm_minus_one"))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revb_s16_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revb_s16_z.c new file mode 100644 index 000000000000..8ac0941881ed --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revb_s16_z.c @@ -0,0 +1,30 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** revb_s16_z_tied1: +** revb z0\.h, p0/z, z0\.h +** ret +*/ +TEST_UNIFORM_Z (revb_s16_z_tied1, svint16_t, + z0 = svrevb_s16_z (p0, z0), + z0 = svrevb_z (p0, z0)) + +/* +** revb_s16_z_untied: +** revb z0\.h, p0/z, z1\.h +** ret +*/ +TEST_UNIFORM_Z (revb_s16_z_untied, svint16_t, + z0 = svrevb_s16_z (p0, z1), + z0 = svrevb_z (p0, z1)) + + diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revb_s32_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revb_s32_z.c new file mode 100644 index 000000000000..f6f1cd7e4017 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revb_s32_z.c @@ -0,0 +1,28 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** revb_s32_z_tied1: +** revb z0\.s, p0/z, z0\.s +** ret +*/ +TEST_UNIFORM_Z (revb_s32_z_tied1, svint32_t, + z0 = svrevb_s32_z (p0, z0), + z0 = svrevb_z (p0, z0)) + +/* +** revb_s32_z_untied: +** revb z0\.s, p0/z, z1\.s +** ret +*/ +TEST_UNIFORM_Z (revb_s32_z_untied, svint32_t, + z0 = svrevb_s32_z (p0, z1), + z0 = svrevb_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revb_s64_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revb_s64_z.c new file mode 100644 index 000000000000..4ebcc4b68d6e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revb_s64_z.c @@ -0,0 +1,28 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** revb_s64_z_tied1: +** revb z0\.d, p0/z, z0\.d +** ret +*/ +TEST_UNIFORM_Z (revb_s64_z_tied1, svint64_t, + z0 = svrevb_s64_z (p0, z0), + z0 = svrevb_z (p0, z0)) + +/* +** revb_s64_z_untied: +** revb z0\.d, p0/z, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revb_s64_z_untied, svint64_t, + z0 = svrevb_s64_z (p0, z1), + z0 = svrevb_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revb_u16_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revb_u16_z.c new file mode 100644 index 000000000000..c54f18cef3d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revb_u16_z.c @@ -0,0 +1,28 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** revb_u16_z_tied1: +** revb z0\.h, p0/z, z0\.h +** ret +*/ +TEST_UNIFORM_Z (revb_u16_z_tied1, svuint16_t, + z0 = svrevb_u16_z (p0, z0), + z0 = svrevb_z (p0, z0)) + +/* +** revb_u16_z_untied: +** revb z0\.h, p0/z, z1\.h +** ret +*/ +TEST_UNIFORM_Z (revb_u16_z_untied, svuint16_t, + z0 = svrevb_u16_z (p0, z1), + z0 = svrevb_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revb_u32_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revb_u32_z.c new file mode 100644 index 000000000000..db72f311d665 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revb_u32_z.c @@ -0,0 +1,28 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** revb_u32_z_tied1: +** revb z0\.s, p0/z, z0\.s +** ret +*/ +TEST_UNIFORM_Z (revb_u32_z_tied1, svuint32_t, + z0 = svrevb_u32_z (p0, z0), + z0 = svrevb_z (p0, z0)) + +/* +** revb_u32_z_untied: +** revb z0\.s, p0/z, z1\.s +** ret +*/ +TEST_UNIFORM_Z (revb_u32_z_untied, svuint32_t, + z0 = svrevb_u32_z (p0, z1), + z0 = svrevb_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revb_u64_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revb_u64_z.c new file mode 100644 index 000000000000..c20d3334eb0e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revb_u64_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** revb_u64_z_tied1: +** revb z0\.d, p0/z, z0\.d +** ret +*/ +TEST_UNIFORM_Z (revb_u64_z_tied1, svuint64_t, + z0 = svrevb_u64_z (p0, z0), + z0 = svrevb_z (p0, z0)) + +/* +** revb_u64_z_untied: +** revb z0\.d, p0/z, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revb_u64_z_untied, svuint64_t, + z0 = svrevb_u64_z (p0, z1), + z0 = svrevb_z (p0, z1)) + diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_bf16_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_bf16_z.c new file mode 100644 index 000000000000..71f269c69ae8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_bf16_z.c @@ -0,0 +1,28 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** revd_bf16_z_tied1: +** revd z0\.q, p0/z, z0\.q +** ret +*/ +TEST_UNIFORM_Z (revd_bf16_z_tied1, svbfloat16_t, + z0 = svrevd_bf16_z (p0, z0), + z0 = svrevd_z (p0, z0)) + +/* +** revd_bf16_z_untied: +** revd z0\.q, p0/z, z1\.q +** ret +*/ +TEST_UNIFORM_Z (revd_bf16_z_untied, svbfloat16_t, + z0 = svrevd_bf16_z (p0, z1), + z0 = svrevd_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_f16_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_f16_z.c new file mode 100644 index 000000000000..8ac612dad9c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_f16_z.c @@ -0,0 +1,28 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** revd_f16_z_tied1: +** revd z0\.q, p0/z, z0\.q +** ret +*/ +TEST_UNIFORM_Z (revd_f16_z_tied1, svfloat16_t, + z0 = svrevd_f16_z (p0, z0), + z0 = svrevd_z (p0, z0)) + +/* +** revd_f16_z_untied: +** revd z0\.q, p0/z, z1\.q +** ret +*/ +TEST_UNIFORM_Z (revd_f16_z_untied, svfloat16_t, + z0 = svrevd_f16_z (p0, z1), + z0 = svrevd_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_f32_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_f32_z.c new file mode 100644 index 000000000000..f44f05563901 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_f32_z.c @@ -0,0 +1,28 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** revd_f32_z_tied1: +** revd z0\.q, p0/z, z0\.q +** ret +*/ +TEST_UNIFORM_Z (revd_f32_z_tied1, svfloat32_t, + z0 = svrevd_f32_z (p0, z0), + z0 = svrevd_z (p0, z0)) + +/* +** revd_f32_z_untied: +** revd z0\.q, p0/z, z1\.q +** ret +*/ +TEST_UNIFORM_Z (revd_f32_z_untied, svfloat32_t, + z0 = svrevd_f32_z (p0, z1), + z0 = svrevd_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_f64_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_f64_z.c new file mode 100644 index 000000000000..2018e0dbc6d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_f64_z.c @@ -0,0 +1,28 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** revd_f64_z_tied1: +** revd z0\.q, p0/z, z0\.q +** ret +*/ +TEST_UNIFORM_Z (revd_f64_z_tied1, svfloat64_t, + z0 = svrevd_f64_z (p0, z0), + z0 = svrevd_z (p0, z0)) + +/* +** revd_f64_z_untied: +** revd z0\.q, p0/z, z1\.q +** ret +*/ +TEST_UNIFORM_Z (revd_f64_z_untied, svfloat64_t, + z0 = svrevd_f64_z (p0, z1), + z0 = svrevd_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_s16_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_s16_z.c new file mode 100644 index 000000000000..44bb8cbfee6f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_s16_z.c @@ -0,0 +1,28 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** revd_s16_z_tied1: +** revd z0\.q, p0/z, z0\.q +** ret +*/ +TEST_UNIFORM_Z (revd_s16_z_tied1, svint16_t, + z0 = svrevd_s16_z (p0, z0), + z0 = svrevd_z (p0, z0)) + +/* +** revd_s16_z_untied: +** revd z0\.q, p0/z, z1\.q +** ret +*/ +TEST_UNIFORM_Z (revd_s16_z_untied, svint16_t, + z0 = svrevd_s16_z (p0, z1), + z0 = svrevd_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_s32_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_s32_z.c new file mode 100644 index 000000000000..79469764aab4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_s32_z.c @@ -0,0 +1,28 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** revd_s32_z_tied1: +** revd z0\.q, p0/z, z0\.q +** ret +*/ +TEST_UNIFORM_Z (revd_s32_z_tied1, svint32_t, + z0 = svrevd_s32_z (p0, z0), + z0 = svrevd_z (p0, z0)) + +/* +** revd_s32_z_untied: +** revd z0\.q, p0/z, z1\.q +** ret +*/ +TEST_UNIFORM_Z (revd_s32_z_untied, svint32_t, + z0 = svrevd_s32_z (p0, z1), + z0 = svrevd_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_s64_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_s64_z.c new file mode 100644 index 000000000000..e6b1e8ca641f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_s64_z.c @@ -0,0 +1,28 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** revd_s64_z_tied1: +** revd z0\.q, p0/z, z0\.q +** ret +*/ +TEST_UNIFORM_Z (revd_s64_z_tied1, svint64_t, + z0 = svrevd_s64_z (p0, z0), + z0 = svrevd_z (p0, z0)) + +/* +** revd_s64_z_untied: +** revd z0\.q, p0/z, z1\.q +** ret +*/ +TEST_UNIFORM_Z (revd_s64_z_untied, svint64_t, + z0 = svrevd_s64_z (p0, z1), + z0 = svrevd_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_s8_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_s8_z.c new file mode 100644 index 000000000000..7f204d70a8f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_s8_z.c @@ -0,0 +1,28 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** revd_s8_z_tied1: +** revd z0\.q, p0/z, z0\.q +** ret +*/ +TEST_UNIFORM_Z (revd_s8_z_tied1, svint8_t, + z0 = svrevd_s8_z (p0, z0), + z0 = svrevd_z (p0, z0)) + +/* +** revd_s8_z_untied: +** revd z0\.q, p0/z, z1\.q +** ret +*/ +TEST_UNIFORM_Z (revd_s8_z_untied, svint8_t, + z0 = svrevd_s8_z (p0, z1), + z0 = svrevd_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_u16_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_u16_z.c new file mode 100644 index 000000000000..6fd565d4f6c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_u16_z.c @@ -0,0 +1,28 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** revd_u16_z_tied1: +** revd z0\.q, p0/z, z0\.q +** ret +*/ +TEST_UNIFORM_Z (revd_u16_z_tied1, svuint16_t, + z0 = svrevd_u16_z (p0, z0), + z0 = svrevd_z (p0, z0)) + +/* +** revd_u16_z_untied: +** revd z0\.q, p0/z, z1\.q +** ret +*/ +TEST_UNIFORM_Z (revd_u16_z_untied, svuint16_t, + z0 = svrevd_u16_z (p0, z1), + z0 = svrevd_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_u32_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_u32_z.c new file mode 100644 index 000000000000..b828aa75aa17 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_u32_z.c @@ -0,0 +1,28 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** revd_u32_z_tied1: +** revd z0\.q, p0/z, z0\.q +** ret +*/ +TEST_UNIFORM_Z (revd_u32_z_tied1, svuint32_t, + z0 = svrevd_u32_z (p0, z0), + z0 = svrevd_z (p0, z0)) + +/* +** revd_u32_z_untied: +** revd z0\.q, p0/z, z1\.q +** ret +*/ +TEST_UNIFORM_Z (revd_u32_z_untied, svuint32_t, + z0 = svrevd_u32_z (p0, z1), + z0 = svrevd_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_u64_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_u64_z.c new file mode 100644 index 000000000000..6c5b1669eacd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_u64_z.c @@ -0,0 +1,28 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** revd_u64_z_tied1: +** revd z0\.q, p0/z, z0\.q +** ret +*/ +TEST_UNIFORM_Z (revd_u64_z_tied1, svuint64_t, + z0 = svrevd_u64_z (p0, z0), + z0 = svrevd_z (p0, z0)) + +/* +** revd_u64_z_untied: +** revd z0\.q, p0/z, z1\.q +** ret +*/ +TEST_UNIFORM_Z (revd_u64_z_untied, svuint64_t, + z0 = svrevd_u64_z (p0, z1), + z0 = svrevd_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_u8_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_u8_z.c new file mode 100644 index 000000000000..30799704cfe9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_u8_z.c @@ -0,0 +1,28 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** revd_u8_z_tied1: +** revd z0\.q, p0/z, z0\.q +** ret +*/ +TEST_UNIFORM_Z (revd_u8_z_tied1, svuint8_t, + z0 = svrevd_u8_z (p0, z0), + z0 = svrevd_z (p0, z0)) + +/* +** revd_u8_z_untied: +** revd z0\.q, p0/z, z1\.q +** ret +*/ +TEST_UNIFORM_Z (revd_u8_z_untied, svuint8_t, + z0 = svrevd_u8_z (p0, z1), + z0 = svrevd_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revh_s32_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revh_s32_z.c new file mode 100644 index 000000000000..ac628c2dd4f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revh_s32_z.c @@ -0,0 +1,30 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** revh_s32_z_tied1: +** revh z0\.s, p0/z, z0\.s +** ret +*/ +TEST_UNIFORM_Z (revh_s32_z_tied1, svint32_t, + z0 = svrevh_s32_z (p0, z0), + z0 = svrevh_z (p0, z0)) + +/* +** revh_s32_z_untied: +** revh z0\.s, p0/z, z1\.s +** ret +*/ +TEST_UNIFORM_Z (revh_s32_z_untied, svint32_t, + z0 = svrevh_s32_z (p0, z1), + z0 = svrevh_z (p0, z1)) + + diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revh_s64_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revh_s64_z.c new file mode 100644 index 000000000000..7e44e8481901 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revh_s64_z.c @@ -0,0 +1,28 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** revh_s64_z_tied1: +** revh z0\.d, p0/z, z0\.d +** ret +*/ +TEST_UNIFORM_Z (revh_s64_z_tied1, svint64_t, + z0 = svrevh_s64_z (p0, z0), + z0 = svrevh_z (p0, z0)) + +/* +** revh_s64_z_untied: +** revh z0\.d, p0/z, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revh_s64_z_untied, svint64_t, + z0 = svrevh_s64_z (p0, z1), + z0 = svrevh_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revh_u32_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revh_u32_z.c new file mode 100644 index 000000000000..d127f869a913 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revh_u32_z.c @@ -0,0 +1,28 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** revh_u32_z_tied1: +** revh z0\.s, p0/z, z0\.s +** ret +*/ +TEST_UNIFORM_Z (revh_u32_z_tied1, svuint32_t, + z0 = svrevh_u32_z (p0, z0), + z0 = svrevh_z (p0, z0)) + +/* +** revh_u32_z_untied: +** revh z0\.s, p0/z, z1\.s +** ret +*/ +TEST_UNIFORM_Z (revh_u32_z_untied, svuint32_t, + z0 = svrevh_u32_z (p0, z1), + z0 = svrevh_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revh_u64_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revh_u64_z.c new file mode 100644 index 000000000000..9aeeec386fdb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revh_u64_z.c @@ -0,0 +1,30 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** revh_u64_z_tied1: +** revh z0\.d, p0/z, z0\.d +** ret +*/ +TEST_UNIFORM_Z (revh_u64_z_tied1, svuint64_t, + z0 = svrevh_u64_z (p0, z0), + z0 = svrevh_z (p0, z0)) + +/* +** revh_u64_z_untied: +** revh z0\.d, p0/z, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revh_u64_z_untied, svuint64_t, + z0 = svrevh_u64_z (p0, z1), + z0 = svrevh_z (p0, z1)) + + diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revw_s64_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revw_s64_z.c new file mode 100644 index 000000000000..ef838873c7e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revw_s64_z.c @@ -0,0 +1,28 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** revw_s64_z_tied1: +** revw z0\.d, p0/z, z0\.d +** ret +*/ +TEST_UNIFORM_Z (revw_s64_z_tied1, svint64_t, + z0 = svrevw_s64_z (p0, z0), + z0 = svrevw_z (p0, z0)) + +/* +** revw_s64_z_untied: +** revw z0\.d, p0/z, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revw_s64_z_untied, svint64_t, + z0 = svrevw_s64_z (p0, z1), + z0 = svrevw_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revw_u64_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revw_u64_z.c new file mode 100644 index 000000000000..c4f27fda6f73 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revw_u64_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** revw_u64_z_tied1: +** revw z0\.d, p0/z, z0\.d +** ret +*/ +TEST_UNIFORM_Z (revw_u64_z_tied1, svuint64_t, + z0 = svrevw_u64_z (p0, z0), + z0 = svrevw_z (p0, z0)) + +/* +** revw_u64_z_untied: +** revw z0\.d, p0/z, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revw_u64_z_untied, svuint64_t, + z0 = svrevw_u64_z (p0, z1), + z0 = svrevw_z (p0, z1)) +
