https://gcc.gnu.org/g:52756251f755dc8aefe44e5026e555c93b2c783b
commit r17-973-g52756251f755dc8aefe44e5026e555c93b2c783b Author: Artemiy Volkov <[email protected]> Date: Fri Jan 9 19:05:28 2026 +0000 aarch64: add zeroing forms for predicated SVE FP unary operations SVE2.2 (or in streaming mode, SME2.2) adds support for zeroing predication for the following floating-point unary instructions: SVE: - FABS (Floating-point absolute value (predicated)) - FNEG (Floating-point negate (predicated)) - FRECPX (Floating-point reciprocal exponent (predicated)) - FRINT<r> (Floating-point round to integral value (predicated)) - FSQRT (Floating-point square root (predicated)) SVE2: - FLOGB (Floating-point base 2 logarithm as integer (predicated)) These instructions are covered by SVE_COND_FP_UNARY for SVE and SVE2_COND_INT_UNARY_FP for SVE2, thus this change is limited to two patterns in each of aarch64-sve.md and aarch64-sve2.md (one for relaxed, and one for strict FP semantics). The change is to add a new alternative with Dz as operand 3 (the merge operand), enabled only if the sve2p2_or_sme2p2 condition holds and emitting a single instruction with zeroing predication. The tests that have been added are based on the original SVE tests for corresponding instructions, but all have a "_z" suffix in their name since they only test codegen for the "_z" variants of the corresponding intrinsics. gcc/ChangeLog: * config/aarch64/aarch64-sve.md (*cond_<optab><mode>_any_relaxed): New alternative for zeroing predication. Add `arch` attribute to every alternative. (*cond_<optab><mode>_any_strict): Likewise. * config/aarch64/aarch64-sve2.md (*cond_<sve_fp_op><mode>): Likewise. (*cond_<sve_fp_op><mode>_strict): Likewise. gcc/testsuite/ChangeLog: * gcc.target/aarch64/sve2/acle/asm/abs_f16_z.c: New test. * gcc.target/aarch64/sve2/acle/asm/abs_f32_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/abs_f64_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/logb_f16_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/logb_f32_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/logb_f64_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/neg_f16_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/neg_f32_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/neg_f64_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/recpx_f16_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/recpx_f32_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/recpx_f64_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rinta_f16_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rinta_f32_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rinta_f64_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rinti_f16_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rinti_f32_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rinti_f64_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rintm_f16_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rintm_f32_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rintm_f64_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rintn_f16_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rintn_f32_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rintn_f64_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rintp_f16_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rintp_f32_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rintp_f64_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rintx_f16_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rintx_f32_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rintx_f64_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rintz_f16_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rintz_f32_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rintz_f64_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sqrt_f16_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sqrt_f32_z.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sqrt_f64_z.c: Likewise. Diff: --- gcc/config/aarch64/aarch64-sve.md | 18 +++++++------ gcc/config/aarch64/aarch64-sve2.md | 18 +++++++------ .../gcc.target/aarch64/sve2/acle/asm/abs_f16_z.c | 30 ++++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/abs_f32_z.c | 30 ++++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/abs_f64_z.c | 30 ++++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/logb_f16_z.c | 19 ++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/logb_f32_z.c | 19 ++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/logb_f64_z.c | 19 ++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/neg_f16_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/neg_f32_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/neg_f64_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/recpx_f16_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/recpx_f32_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/recpx_f64_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rinta_f16_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rinta_f32_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rinta_f64_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rinti_f16_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rinti_f32_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rinti_f64_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rintm_f16_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rintm_f32_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rintm_f64_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rintn_f16_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rintn_f32_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rintn_f64_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rintp_f16_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rintp_f32_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rintp_f64_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rintx_f16_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rintx_f32_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rintx_f64_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rintz_f16_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rintz_f32_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/rintz_f64_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/sqrt_f16_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/sqrt_f32_z.c | 29 +++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/sqrt_f64_z.c | 29 +++++++++++++++++++++ 38 files changed, 1037 insertions(+), 16 deletions(-) diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 8e4fc05e63fa..6e664e738428 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -4110,10 +4110,11 @@ (match_operand:SVE_F 3 "aarch64_simd_reg_or_zero")] UNSPEC_SEL))] "TARGET_SVE && !rtx_equal_p (operands[2], operands[3])" - {@ [ cons: =0 , 1 , 2 , 3 ; attrs: movprfx ] - [ &w , Upl , w , 0 ; * ] <sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype> - [ ?&w , Upl , w , Dz ; yes ] movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;<sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype> - [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %3\;<sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype> + {@ [ cons: =0 , 1 , 2 , 3 ; attrs: movprfx, arch ] + [ &w , Upl , w , 0 ; * , * ] <sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype> + [ &w , Upl , w , Dz ; * , sve2p2_or_sme2p2 ] <sve_fp_op>\t%0.<Vetype>, %1/z, %2.<Vetype> + [ ?&w , Upl , w , Dz ; yes , * ] movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;<sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype> + [ ?&w , Upl , w , w ; yes , * ] movprfx\t%0, %3\;<sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype> } "&& !rtx_equal_p (operands[1], operands[4])" { @@ -4134,10 +4135,11 @@ (match_operand:SVE_FULL_F 3 "aarch64_simd_reg_or_zero")] UNSPEC_SEL))] "TARGET_SVE && !rtx_equal_p (operands[2], operands[3])" - {@ [ cons: =0 , 1 , 2 , 3 ; attrs: movprfx ] - [ &w , Upl , w , 0 ; * ] <sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype> - [ ?&w , Upl , w , Dz ; yes ] movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;<sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype> - [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %3\;<sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype> + {@ [ cons: =0 , 1 , 2 , 3 ; attrs: movprfx, arch ] + [ &w , Upl , w , 0 ; * , * ] <sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype> + [ &w , Upl , w , Dz ; * , sve2p2_or_sme2p2 ] <sve_fp_op>\t%0.<Vetype>, %1/z, %2.<Vetype> + [ ?&w , Upl , w , Dz ; yes , * ] movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;<sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype> + [ ?&w , Upl , w , w ; yes , * ] movprfx\t%0, %3\;<sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype> } [(set_attr "sve_type" "sve_<sve_type_unspec>")] ) diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md index 2045b09e05b9..f4e8709cb522 100644 --- a/gcc/config/aarch64/aarch64-sve2.md +++ b/gcc/config/aarch64/aarch64-sve2.md @@ -3916,10 +3916,11 @@ (match_operand:<V_INT_EQUIV> 3 "aarch64_simd_reg_or_zero")] UNSPEC_SEL))] "TARGET_SVE2 && !rtx_equal_p (operands[2], operands[3])" - {@ [ cons: =0 , 1 , 2 , 3 ; attrs: movprfx ] - [ &w , Upl , w , 0 ; * ] <sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype> - [ ?&w , Upl , w , Dz ; yes ] movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;<sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype> - [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %3\;<sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype> + {@ [ cons: =0 , 1 , 2 , 3 ; attrs: movprfx, arch ] + [ &w , Upl , w , 0 ; * , * ] <sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype> + [ &w , Upl , w , Dz ; * , sve2p2_or_sme2p2 ] <sve_fp_op>\t%0.<Vetype>, %1/z, %2.<Vetype> + [ ?&w , Upl , w , Dz ; yes , * ] movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;<sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype> + [ ?&w , Upl , w , w ; yes , * ] movprfx\t%0, %3\;<sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype> } "&& !rtx_equal_p (operands[1], operands[4])" { @@ -3940,10 +3941,11 @@ (match_operand:<V_INT_EQUIV> 3 "aarch64_simd_reg_or_zero")] UNSPEC_SEL))] "TARGET_SVE2 && !rtx_equal_p (operands[2], operands[3])" - {@ [ cons: =0 , 1 , 2 , 3 ; attrs: movprfx ] - [ &w , Upl , w , 0 ; * ] <sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype> - [ ?&w , Upl , w , Dz ; yes ] movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;<sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype> - [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %3\;<sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype> + {@ [ cons: =0 , 1 , 2 , 3 ; attrs: movprfx, arch ] + [ &w , Upl , w , 0 ; * , * ] <sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype> + [ &w , Upl , w , Dz ; * , sve2p2_or_sme2p2 ] <sve_fp_op>\t%0.<Vetype>, %1/z, %2.<Vetype> + [ ?&w , Upl , w , Dz ; yes , * ] movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;<sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype> + [ ?&w , Upl , w , w ; yes , * ] movprfx\t%0, %3\;<sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype> } [(set_attr "sve_type" "sve_fp_log")] ) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abs_f16_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abs_f16_z.c new file mode 100644 index 000000000000..b3a6f62051bd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abs_f16_z.c @@ -0,0 +1,30 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** abs_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** fabs z0\.h, p0/z, \1\.h +** ret +*/ +TEST_UNIFORM_Z (abs_f16_z_tied1, svfloat16_t, + z0 = svabs_f16_z (p0, z0), + z0 = svabs_z (p0, z0)) + +/* +** abs_f16_z_untied: +** fabs z0\.h, p0/z, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abs_f16_z_untied, svfloat16_t, + z0 = svabs_f16_z (p0, z1), + z0 = svabs_z (p0, z1)) + diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abs_f32_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abs_f32_z.c new file mode 100644 index 000000000000..1ee505267f61 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abs_f32_z.c @@ -0,0 +1,30 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** abs_f32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** fabs z0\.s, p0/z, \1\.s +** ret +*/ +TEST_UNIFORM_Z (abs_f32_z_tied1, svfloat32_t, + z0 = svabs_f32_z (p0, z0), + z0 = svabs_z (p0, z0)) + +/* +** abs_f32_z_untied: +** fabs z0\.s, p0/z, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abs_f32_z_untied, svfloat32_t, + z0 = svabs_f32_z (p0, z1), + z0 = svabs_z (p0, z1)) + diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abs_f64_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abs_f64_z.c new file mode 100644 index 000000000000..c5df18d781df --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abs_f64_z.c @@ -0,0 +1,30 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** abs_f64_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** fabs z0\.d, p0/z, \1\.d +** ret +*/ +TEST_UNIFORM_Z (abs_f64_z_tied1, svfloat64_t, + z0 = svabs_f64_z (p0, z0), + z0 = svabs_z (p0, z0)) + +/* +** abs_f64_z_untied: +** fabs z0\.d, p0/z, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abs_f64_z_untied, svfloat64_t, + z0 = svabs_f64_z (p0, z1), + z0 = svabs_z (p0, z1)) + diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/logb_f16_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/logb_f16_z.c new file mode 100644 index 000000000000..ca4248ffa9c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/logb_f16_z.c @@ -0,0 +1,19 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** logb_f16_z: +** flogb z0\.h, p0/z, z4\.h +** ret +*/ +TEST_DUAL_Z (logb_f16_z, svint16_t, svfloat16_t, + z0 = svlogb_f16_z (p0, z4), + z0 = svlogb_z (p0, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/logb_f32_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/logb_f32_z.c new file mode 100644 index 000000000000..bb94b79120f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/logb_f32_z.c @@ -0,0 +1,19 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** logb_f32_z: +** flogb z0\.s, p0/z, z4\.s +** ret +*/ +TEST_DUAL_Z (logb_f32_z, svint32_t, svfloat32_t, + z0 = svlogb_f32_z (p0, z4), + z0 = svlogb_z (p0, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/logb_f64_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/logb_f64_z.c new file mode 100644 index 000000000000..5881b3ac1bba --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/logb_f64_z.c @@ -0,0 +1,19 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** logb_f64_z: +** flogb z0\.d, p0/z, z4\.d +** ret +*/ +TEST_DUAL_Z (logb_f64_z, svint64_t, svfloat64_t, + z0 = svlogb_f64_z (p0, z4), + z0 = svlogb_z (p0, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/neg_f16_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/neg_f16_z.c new file mode 100644 index 000000000000..5cdd771b3861 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/neg_f16_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** neg_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** fneg z0\.h, p0/z, \1\.h +** ret +*/ +TEST_UNIFORM_Z (neg_f16_z_tied1, svfloat16_t, + z0 = svneg_f16_z (p0, z0), + z0 = svneg_z (p0, z0)) + +/* +** neg_f16_z_untied: +** fneg z0\.h, p0/z, z1\.h +** ret +*/ +TEST_UNIFORM_Z (neg_f16_z_untied, svfloat16_t, + z0 = svneg_f16_z (p0, z1), + z0 = svneg_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/neg_f32_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/neg_f32_z.c new file mode 100644 index 000000000000..0be195194674 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/neg_f32_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** neg_f32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** fneg z0\.s, p0/z, \1\.s +** ret +*/ +TEST_UNIFORM_Z (neg_f32_z_tied1, svfloat32_t, + z0 = svneg_f32_z (p0, z0), + z0 = svneg_z (p0, z0)) + +/* +** neg_f32_z_untied: +** fneg z0\.s, p0/z, z1\.s +** ret +*/ +TEST_UNIFORM_Z (neg_f32_z_untied, svfloat32_t, + z0 = svneg_f32_z (p0, z1), + z0 = svneg_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/neg_f64_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/neg_f64_z.c new file mode 100644 index 000000000000..9c5a2b50426f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/neg_f64_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** neg_f64_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** fneg z0\.d, p0/z, \1\.d +** ret +*/ +TEST_UNIFORM_Z (neg_f64_z_tied1, svfloat64_t, + z0 = svneg_f64_z (p0, z0), + z0 = svneg_z (p0, z0)) + +/* +** neg_f64_z_untied: +** fneg z0\.d, p0/z, z1\.d +** ret +*/ +TEST_UNIFORM_Z (neg_f64_z_untied, svfloat64_t, + z0 = svneg_f64_z (p0, z1), + z0 = svneg_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/recpx_f16_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/recpx_f16_z.c new file mode 100644 index 000000000000..e4a889864bbc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/recpx_f16_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** recpx_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** frecpx z0\.h, p0/z, \1\.h +** ret +*/ +TEST_UNIFORM_Z (recpx_f16_z_tied1, svfloat16_t, + z0 = svrecpx_f16_z (p0, z0), + z0 = svrecpx_z (p0, z0)) + +/* +** recpx_f16_z_untied: +** frecpx z0\.h, p0/z, z1\.h +** ret +*/ +TEST_UNIFORM_Z (recpx_f16_z_untied, svfloat16_t, + z0 = svrecpx_f16_z (p0, z1), + z0 = svrecpx_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/recpx_f32_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/recpx_f32_z.c new file mode 100644 index 000000000000..f75524d490c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/recpx_f32_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** recpx_f32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** frecpx z0\.s, p0/z, \1\.s +** ret +*/ +TEST_UNIFORM_Z (recpx_f32_z_tied1, svfloat32_t, + z0 = svrecpx_f32_z (p0, z0), + z0 = svrecpx_z (p0, z0)) + +/* +** recpx_f32_z_untied: +** frecpx z0\.s, p0/z, z1\.s +** ret +*/ +TEST_UNIFORM_Z (recpx_f32_z_untied, svfloat32_t, + z0 = svrecpx_f32_z (p0, z1), + z0 = svrecpx_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/recpx_f64_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/recpx_f64_z.c new file mode 100644 index 000000000000..04926f4a4940 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/recpx_f64_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** recpx_f64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** frecpx z0\.d, p0/z, \1 +** ret +*/ +TEST_UNIFORM_Z (recpx_f64_z_tied1, svfloat64_t, + z0 = svrecpx_f64_z (p0, z0), + z0 = svrecpx_z (p0, z0)) + +/* +** recpx_f64_z_untied: +** frecpx z0\.d, p0/z, z1\.d +** ret +*/ +TEST_UNIFORM_Z (recpx_f64_z_untied, svfloat64_t, + z0 = svrecpx_f64_z (p0, z1), + z0 = svrecpx_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rinta_f16_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rinta_f16_z.c new file mode 100644 index 000000000000..030e796f954d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rinta_f16_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rinta_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** frinta z0\.h, p0/z, \1\.h +** ret +*/ +TEST_UNIFORM_Z (rinta_f16_z_tied1, svfloat16_t, + z0 = svrinta_f16_z (p0, z0), + z0 = svrinta_z (p0, z0)) + +/* +** rinta_f16_z_untied: +** frinta z0\.h, p0/z, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rinta_f16_z_untied, svfloat16_t, + z0 = svrinta_f16_z (p0, z1), + z0 = svrinta_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rinta_f32_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rinta_f32_z.c new file mode 100644 index 000000000000..8cdec1ec4ed9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rinta_f32_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rinta_f32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** frinta z0\.s, p0/z, \1\.s +** ret +*/ +TEST_UNIFORM_Z (rinta_f32_z_tied1, svfloat32_t, + z0 = svrinta_f32_z (p0, z0), + z0 = svrinta_z (p0, z0)) + +/* +** rinta_f32_z_untied: +** frinta z0\.s, p0/z, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rinta_f32_z_untied, svfloat32_t, + z0 = svrinta_f32_z (p0, z1), + z0 = svrinta_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rinta_f64_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rinta_f64_z.c new file mode 100644 index 000000000000..72bcbe424c95 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rinta_f64_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rinta_f64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** frinta z0\.d, p0/z, \1 +** ret +*/ +TEST_UNIFORM_Z (rinta_f64_z_tied1, svfloat64_t, + z0 = svrinta_f64_z (p0, z0), + z0 = svrinta_z (p0, z0)) + +/* +** rinta_f64_z_untied: +** frinta z0\.d, p0/z, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rinta_f64_z_untied, svfloat64_t, + z0 = svrinta_f64_z (p0, z1), + z0 = svrinta_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rinti_f16_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rinti_f16_z.c new file mode 100644 index 000000000000..43af2048b77e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rinti_f16_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rinti_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** frinti z0\.h, p0/z, \1\.h +** ret +*/ +TEST_UNIFORM_Z (rinti_f16_z_tied1, svfloat16_t, + z0 = svrinti_f16_z (p0, z0), + z0 = svrinti_z (p0, z0)) + +/* +** rinti_f16_z_untied: +** frinti z0\.h, p0/z, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rinti_f16_z_untied, svfloat16_t, + z0 = svrinti_f16_z (p0, z1), + z0 = svrinti_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rinti_f32_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rinti_f32_z.c new file mode 100644 index 000000000000..0ed266b99788 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rinti_f32_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rinti_f32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** frinti z0\.s, p0/z, \1\.s +** ret +*/ +TEST_UNIFORM_Z (rinti_f32_z_tied1, svfloat32_t, + z0 = svrinti_f32_z (p0, z0), + z0 = svrinti_z (p0, z0)) + +/* +** rinti_f32_z_untied: +** frinti z0\.s, p0/z, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rinti_f32_z_untied, svfloat32_t, + z0 = svrinti_f32_z (p0, z1), + z0 = svrinti_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rinti_f64_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rinti_f64_z.c new file mode 100644 index 000000000000..20dc75b5357a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rinti_f64_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rinti_f64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** frinti z0\.d, p0/z, \1 +** ret +*/ +TEST_UNIFORM_Z (rinti_f64_z_tied1, svfloat64_t, + z0 = svrinti_f64_z (p0, z0), + z0 = svrinti_z (p0, z0)) + +/* +** rinti_f64_z_untied: +** frinti z0\.d, p0/z, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rinti_f64_z_untied, svfloat64_t, + z0 = svrinti_f64_z (p0, z1), + z0 = svrinti_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintm_f16_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintm_f16_z.c new file mode 100644 index 000000000000..2825d66bacfb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintm_f16_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rintm_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** frintm z0\.h, p0/z, \1\.h +** ret +*/ +TEST_UNIFORM_Z (rintm_f16_z_tied1, svfloat16_t, + z0 = svrintm_f16_z (p0, z0), + z0 = svrintm_z (p0, z0)) + +/* +** rintm_f16_z_untied: +** frintm z0\.h, p0/z, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rintm_f16_z_untied, svfloat16_t, + z0 = svrintm_f16_z (p0, z1), + z0 = svrintm_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintm_f32_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintm_f32_z.c new file mode 100644 index 000000000000..926612400002 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintm_f32_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rintm_f32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** frintm z0\.s, p0/z, \1\.s +** ret +*/ +TEST_UNIFORM_Z (rintm_f32_z_tied1, svfloat32_t, + z0 = svrintm_f32_z (p0, z0), + z0 = svrintm_z (p0, z0)) + +/* +** rintm_f32_z_untied: +** frintm z0\.s, p0/z, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rintm_f32_z_untied, svfloat32_t, + z0 = svrintm_f32_z (p0, z1), + z0 = svrintm_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintm_f64_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintm_f64_z.c new file mode 100644 index 000000000000..22eaddc7a9e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintm_f64_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rintm_f64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** frintm z0\.d, p0/z, \1 +** ret +*/ +TEST_UNIFORM_Z (rintm_f64_z_tied1, svfloat64_t, + z0 = svrintm_f64_z (p0, z0), + z0 = svrintm_z (p0, z0)) + +/* +** rintm_f64_z_untied: +** frintm z0\.d, p0/z, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rintm_f64_z_untied, svfloat64_t, + z0 = svrintm_f64_z (p0, z1), + z0 = svrintm_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintn_f16_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintn_f16_z.c new file mode 100644 index 000000000000..fc402eec3743 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintn_f16_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rintn_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** frintn z0\.h, p0/z, \1\.h +** ret +*/ +TEST_UNIFORM_Z (rintn_f16_z_tied1, svfloat16_t, + z0 = svrintn_f16_z (p0, z0), + z0 = svrintn_z (p0, z0)) + +/* +** rintn_f16_z_untied: +** frintn z0\.h, p0/z, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rintn_f16_z_untied, svfloat16_t, + z0 = svrintn_f16_z (p0, z1), + z0 = svrintn_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintn_f32_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintn_f32_z.c new file mode 100644 index 000000000000..936621c511bf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintn_f32_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rintn_f32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** frintn z0\.s, p0/z, \1\.s +** ret +*/ +TEST_UNIFORM_Z (rintn_f32_z_tied1, svfloat32_t, + z0 = svrintn_f32_z (p0, z0), + z0 = svrintn_z (p0, z0)) + +/* +** rintn_f32_z_untied: +** frintn z0\.s, p0/z, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rintn_f32_z_untied, svfloat32_t, + z0 = svrintn_f32_z (p0, z1), + z0 = svrintn_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintn_f64_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintn_f64_z.c new file mode 100644 index 000000000000..b149306e8fda --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintn_f64_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rintn_f64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** frintn z0\.d, p0/z, \1 +** ret +*/ +TEST_UNIFORM_Z (rintn_f64_z_tied1, svfloat64_t, + z0 = svrintn_f64_z (p0, z0), + z0 = svrintn_z (p0, z0)) + +/* +** rintn_f64_z_untied: +** frintn z0\.d, p0/z, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rintn_f64_z_untied, svfloat64_t, + z0 = svrintn_f64_z (p0, z1), + z0 = svrintn_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintp_f16_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintp_f16_z.c new file mode 100644 index 000000000000..86af3c4125af --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintp_f16_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rintp_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** frintp z0\.h, p0/z, \1\.h +** ret +*/ +TEST_UNIFORM_Z (rintp_f16_z_tied1, svfloat16_t, + z0 = svrintp_f16_z (p0, z0), + z0 = svrintp_z (p0, z0)) + +/* +** rintp_f16_z_untied: +** frintp z0\.h, p0/z, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rintp_f16_z_untied, svfloat16_t, + z0 = svrintp_f16_z (p0, z1), + z0 = svrintp_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintp_f32_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintp_f32_z.c new file mode 100644 index 000000000000..829d6178d462 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintp_f32_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rintp_f32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** frintp z0\.s, p0/z, \1\.s +** ret +*/ +TEST_UNIFORM_Z (rintp_f32_z_tied1, svfloat32_t, + z0 = svrintp_f32_z (p0, z0), + z0 = svrintp_z (p0, z0)) + +/* +** rintp_f32_z_untied: +** frintp z0\.s, p0/z, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rintp_f32_z_untied, svfloat32_t, + z0 = svrintp_f32_z (p0, z1), + z0 = svrintp_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintp_f64_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintp_f64_z.c new file mode 100644 index 000000000000..3312e618a724 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintp_f64_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rintp_f64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** frintp z0\.d, p0/z, \1 +** ret +*/ +TEST_UNIFORM_Z (rintp_f64_z_tied1, svfloat64_t, + z0 = svrintp_f64_z (p0, z0), + z0 = svrintp_z (p0, z0)) + +/* +** rintp_f64_z_untied: +** frintp z0\.d, p0/z, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rintp_f64_z_untied, svfloat64_t, + z0 = svrintp_f64_z (p0, z1), + z0 = svrintp_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintx_f16_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintx_f16_z.c new file mode 100644 index 000000000000..12d4910f231b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintx_f16_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rintx_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** frintx z0\.h, p0/z, \1\.h +** ret +*/ +TEST_UNIFORM_Z (rintx_f16_z_tied1, svfloat16_t, + z0 = svrintx_f16_z (p0, z0), + z0 = svrintx_z (p0, z0)) + +/* +** rintx_f16_z_untied: +** frintx z0\.h, p0/z, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rintx_f16_z_untied, svfloat16_t, + z0 = svrintx_f16_z (p0, z1), + z0 = svrintx_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintx_f32_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintx_f32_z.c new file mode 100644 index 000000000000..1c00eb1766eb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintx_f32_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rintx_f32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** frintx z0\.s, p0/z, \1\.s +** ret +*/ +TEST_UNIFORM_Z (rintx_f32_z_tied1, svfloat32_t, + z0 = svrintx_f32_z (p0, z0), + z0 = svrintx_z (p0, z0)) + +/* +** rintx_f32_z_untied: +** frintx z0\.s, p0/z, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rintx_f32_z_untied, svfloat32_t, + z0 = svrintx_f32_z (p0, z1), + z0 = svrintx_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintx_f64_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintx_f64_z.c new file mode 100644 index 000000000000..92472d99b7d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintx_f64_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rintx_f64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** frintx z0\.d, p0/z, \1 +** ret +*/ +TEST_UNIFORM_Z (rintx_f64_z_tied1, svfloat64_t, + z0 = svrintx_f64_z (p0, z0), + z0 = svrintx_z (p0, z0)) + +/* +** rintx_f64_z_untied: +** frintx z0\.d, p0/z, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rintx_f64_z_untied, svfloat64_t, + z0 = svrintx_f64_z (p0, z1), + z0 = svrintx_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintz_f16_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintz_f16_z.c new file mode 100644 index 000000000000..e63aefb728a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintz_f16_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rintz_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** frintz z0\.h, p0/z, \1\.h +** ret +*/ +TEST_UNIFORM_Z (rintz_f16_z_tied1, svfloat16_t, + z0 = svrintz_f16_z (p0, z0), + z0 = svrintz_z (p0, z0)) + +/* +** rintz_f16_z_untied: +** frintz z0\.h, p0/z, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rintz_f16_z_untied, svfloat16_t, + z0 = svrintz_f16_z (p0, z1), + z0 = svrintz_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintz_f32_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintz_f32_z.c new file mode 100644 index 000000000000..cc162bd3fcc4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintz_f32_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rintz_f32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** frintz z0\.s, p0/z, \1\.s +** ret +*/ +TEST_UNIFORM_Z (rintz_f32_z_tied1, svfloat32_t, + z0 = svrintz_f32_z (p0, z0), + z0 = svrintz_z (p0, z0)) + +/* +** rintz_f32_z_untied: +** frintz z0\.s, p0/z, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rintz_f32_z_untied, svfloat32_t, + z0 = svrintz_f32_z (p0, z1), + z0 = svrintz_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintz_f64_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintz_f64_z.c new file mode 100644 index 000000000000..e9d8965d5a1a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rintz_f64_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** rintz_f64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** frintz z0\.d, p0/z, \1 +** ret +*/ +TEST_UNIFORM_Z (rintz_f64_z_tied1, svfloat64_t, + z0 = svrintz_f64_z (p0, z0), + z0 = svrintz_z (p0, z0)) + +/* +** rintz_f64_z_untied: +** frintz z0\.d, p0/z, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rintz_f64_z_untied, svfloat64_t, + z0 = svrintz_f64_z (p0, z1), + z0 = svrintz_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sqrt_f16_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sqrt_f16_z.c new file mode 100644 index 000000000000..0ad001d541df --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sqrt_f16_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** sqrt_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** fsqrt z0\.h, p0/z, \1\.h +** ret +*/ +TEST_UNIFORM_Z (sqrt_f16_z_tied1, svfloat16_t, + z0 = svsqrt_f16_z (p0, z0), + z0 = svsqrt_z (p0, z0)) + +/* +** sqrt_f16_z_untied: +** fsqrt z0\.h, p0/z, z1\.h +** ret +*/ +TEST_UNIFORM_Z (sqrt_f16_z_untied, svfloat16_t, + z0 = svsqrt_f16_z (p0, z1), + z0 = svsqrt_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sqrt_f32_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sqrt_f32_z.c new file mode 100644 index 000000000000..1deb5e4013c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sqrt_f32_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** sqrt_f32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** fsqrt z0\.s, p0/z, \1\.s +** ret +*/ +TEST_UNIFORM_Z (sqrt_f32_z_tied1, svfloat32_t, + z0 = svsqrt_f32_z (p0, z0), + z0 = svsqrt_z (p0, z0)) + +/* +** sqrt_f32_z_untied: +** fsqrt z0\.s, p0/z, z1\.s +** ret +*/ +TEST_UNIFORM_Z (sqrt_f32_z_untied, svfloat32_t, + z0 = svsqrt_f32_z (p0, z1), + z0 = svsqrt_z (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sqrt_f64_z.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sqrt_f64_z.c new file mode 100644 index 000000000000..7e36d52f3d16 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sqrt_f64_z.c @@ -0,0 +1,29 @@ +/* { dg-do assemble { target aarch64_asm_sve2p2_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sve2p2_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +#pragma GCC target "+sve2p2" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sme2p2" +#endif + +/* +** sqrt_f64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** fsqrt z0\.d, p0/z, \1 +** ret +*/ +TEST_UNIFORM_Z (sqrt_f64_z_tied1, svfloat64_t, + z0 = svsqrt_f64_z (p0, z0), + z0 = svsqrt_z (p0, z0)) + +/* +** sqrt_f64_z_untied: +** fsqrt z0\.d, p0/z, z1\.d +** ret +*/ +TEST_UNIFORM_Z (sqrt_f64_z_untied, svfloat64_t, + z0 = svsqrt_f64_z (p0, z1), + z0 = svsqrt_z (p0, z1))
