https://gcc.gnu.org/g:1cec26c68d7e742f6db2fc6fa955b463b594e1b6
commit r17-1106-g1cec26c68d7e742f6db2fc6fa955b463b594e1b6 Author: Dhruv Chawla <[email protected]> Date: Tue May 19 13:09:50 2026 +0000 i386: Fix typos in various files Signed-off-by: Dhruv Chawla <[email protected]> gcc/ChangeLog: * config/i386/athlon.md: Fix typos. * config/i386/avx512fintrin.h: Likewise. * config/i386/btver2.md: Likewise. * config/i386/c86-4g-m7.md: Likewise. * config/i386/c86-4g.md: Likewise. * config/i386/cygwin.h: Likewise. * config/i386/i386-c.cc (ix86_target_macros_internal): Likewise. * config/i386/i386-expand.cc (ix86_expand_branch): Likewise. (ix86_expand_int_sse_cmp): Likewise. (ix86_expand_vec_perm): Likewise. (expand_small_cpymem_or_setmem): Likewise. (ix86_copy_addr_to_reg): Likewise. (ix86_expand_special_args_builtin): Likewise. (ix86_expand_vector_init_interleave): Likewise. (expand_vec_perm_shufps_shufps): Likewise. (ix86_expand_sse2_mulvxdi3): Likewise. (ix86_gen_ccmp_first): Likewise. * config/i386/i386-features.cc (general_scalar_to_vector_candidate_p): Likewise. (pass_x86_cse::x86_cse): Likewise. (ix86_apx_nf_convert): Likewise. (dispatch_function_versions): Likewise. * config/i386/i386-features.h (class scalar_chain): Likewise. * config/i386/i386-options.cc (ix86_function_specific_restore): Likewise. (ix86_valid_target_attribute_tree): Likewise. (ix86_override_options_after_change_1): Likewise. (ix86_option_override_internal): Likewise. * config/i386/i386.cc (ix86_can_inline_p): Likewise. (ix86_function_regparm): Likewise. (construct_container): Likewise. (ix86_return_in_memory): Likewise. (output_indirect_thunk): Likewise. (ix86_compute_frame_layout): Likewise. (choose_basereg): Likewise. (ix86_emit_save_reg_using_mov): Likewise. (pro_epilogue_adjust_stack): Likewise. (ix86_expand_prologue): Likewise. (ix86_emit_restore_sse_regs_using_mov): Likewise. (ix86_memory_address_reg_class): Likewise. (ix86_avx_u128_mode_after): Likewise. (ix86_output_addr_diff_elt): Likewise. (ix86_lea_outperforms): Likewise. (ix86_avoid_lea_for_addr): Likewise. (ix86_cc_modes_compatible): Likewise. (add_parameter_dependencies): Likewise. (ix86_data_alignment): Likewise. (ix86_gimple_fold_builtin): Likewise. (ix86_autovectorize_vector_modes): Likewise. (ix86_max_noce_ifcvt_seq_cost): Likewise. (ix86_vector_costs::add_stmt_cost): Likewise. (ix86_vector_costs::finish_cost): Likewise. (ix86_optab_supported_p): Likewise. (ix86_push_rounding): Likewise. * config/i386/i386.h (host_detect_local_cpu): Likewise. (enum reg_class): Likewise. * config/i386/i386.md: Likewise. * config/i386/i386elf.h: Likewise. * config/i386/predicates.md: Likewise. * config/i386/sse.md: Likewise. * config/i386/x86-tune-costs.h (struct processor_costs): Likewise. * config/i386/x86-tune-sched-atom.cc (swap_top_of_ready_list): Likewise. (ix86_atom_sched_reorder): Likewise. * config/i386/x86-tune-sched-bd.cc (find_constant): Likewise. * config/i386/x86-tune-sched.cc (exact_store_load_dependency): Likewise. * config/i386/x86-tune.def (X86_TUNE_FUSE_MOV_AND_ALU): Likewise. (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB): Likewise. (X86_TUNE_DOUBLE_WITH_ADD): Likewise. (X86_TUNE_PROMOTE_QIMODE): Likewise. * config/i386/zn4zn5.md: Likewise. * config/i386/znver.md: Likewise. Diff: --- gcc/config/i386/athlon.md | 22 ++++++------ gcc/config/i386/avx512fintrin.h | 2 +- gcc/config/i386/btver2.md | 12 +++---- gcc/config/i386/c86-4g-m7.md | 4 +-- gcc/config/i386/c86-4g.md | 4 +-- gcc/config/i386/cygwin.h | 4 +-- gcc/config/i386/i386-c.cc | 2 +- gcc/config/i386/i386-expand.cc | 24 ++++++------- gcc/config/i386/i386-features.cc | 10 +++--- gcc/config/i386/i386-features.h | 2 +- gcc/config/i386/i386-options.cc | 8 ++--- gcc/config/i386/i386.cc | 64 +++++++++++++++++----------------- gcc/config/i386/i386.h | 6 ++-- gcc/config/i386/i386.md | 8 ++--- gcc/config/i386/i386elf.h | 2 +- gcc/config/i386/predicates.md | 8 ++--- gcc/config/i386/sse.md | 10 +++--- gcc/config/i386/x86-tune-costs.h | 16 ++++----- gcc/config/i386/x86-tune-sched-atom.cc | 6 ++-- gcc/config/i386/x86-tune-sched-bd.cc | 4 +-- gcc/config/i386/x86-tune-sched.cc | 2 +- gcc/config/i386/x86-tune.def | 8 ++--- gcc/config/i386/zn4zn5.md | 2 +- gcc/config/i386/znver.md | 6 ++-- 24 files changed, 118 insertions(+), 118 deletions(-) diff --git a/gcc/config/i386/athlon.md b/gcc/config/i386/athlon.md index 6d6c50d907d9..5dfb6c3eeef8 100644 --- a/gcc/config/i386/athlon.md +++ b/gcc/config/i386/athlon.md @@ -70,7 +70,7 @@ (define_cpu_unit "athlon-decodev" "athlon") ;; Model the fact that double decoded instruction may take 2 cycles ;; to decode when decoder2 and decoder0 in next cycle -;; is used (this is needed to allow troughput of 1.5 double decoded +;; is used (this is needed to allow throughput of 1.5 double decoded ;; instructions per cycle). ;; ;; In order to avoid dependence between reservation of decoder @@ -397,7 +397,7 @@ "athlon-vector,(athlon-ieu+athlon-agu),athlon-ieu, athlon-store") -;; Athlon floatin point unit +;; Athlon floating point unit (define_insn_reservation "athlon_fldxf" 12 (and (eq_attr "cpu" "athlon") (and (eq_attr "type" "fmov") @@ -903,7 +903,7 @@ (eq_attr "mode" "V2DF,V4SF,TI")))) "athlon-direct,athlon-fpsched,athlon-fstore") ;; cvtsi2sd mem,reg is directpath path (cvtsi2sd reg,reg is doublepath) -;; cvtsi2sd has troughput 1 and is executed in store unit with latency of 6 +;; cvtsi2sd has throughput 1 and is executed in store unit with latency of 6 (define_insn_reservation "athlon_sseicvt_cvtsi2sd_load" 6 (and (eq_attr "cpu" "athlon,k8") (and (eq_attr "type" "sseicvt") @@ -970,7 +970,7 @@ (and (eq_attr "mode" "SF,DF") (eq_attr "memory" "none"))))) "athlon-vector,athlon-fploadk8,(athlon-faddmul+athlon-fstore)") -;; cvtsd2ss mem,reg is doublepath, troughput unknown, latency 9 +;; cvtsd2ss mem,reg is doublepath, throughput unknown, latency 9 (define_insn_reservation "athlon_ssecvt_cvtsd2ss_load_k8" 9 (and (eq_attr "cpu" "k8,athlon") (and (eq_attr "type" "ssecvt") @@ -985,7 +985,7 @@ (and (eq_attr "mode" "SF") (eq_attr "memory" "load"))))) "athlon-double,athlon-fploadk8,(athlon-faddmul+athlon-fstore)") -;; cvtsd2ss reg,reg is vectorpath, troughput unknown, latency 12 +;; cvtsd2ss reg,reg is vectorpath, throughput unknown, latency 12 (define_insn_reservation "athlon_ssecvt_cvtsd2ss" 12 (and (eq_attr "cpu" "athlon,k8") (and (eq_attr "type" "ssecvt") @@ -1014,8 +1014,8 @@ (and (eq_attr "mode" "V4SF,V2DF,TI") (eq_attr "memory" "load"))))) "athlon-double,athlon-fploadk8,(athlon-faddmul+athlon-fstore)") -;; cvtpd2ps mem,reg is vectorpath, troughput unknown, latency 10 -;; ??? Why it is fater than cvtsd2ss? +;; cvtpd2ps mem,reg is vectorpath, throughput unknown, latency 10 +;; ??? Why it is faster than cvtsd2ss? (define_insn_reservation "athlon_ssecvt_cvtpd2ps" 8 (and (eq_attr "cpu" "athlon,k8") (and (eq_attr "type" "ssecvt") @@ -1030,7 +1030,7 @@ (and (eq_attr "mode" "V4SF,V2DF,TI") (eq_attr "memory" "none"))))) "athlon-double,athlon-fpsched,(athlon-faddmul+athlon-fstore)") -;; cvtsd2si mem,reg is doublepath, troughput 1, latency 9 +;; cvtsd2si mem,reg is doublepath, throughput 1, latency 9 (define_insn_reservation "athlon_secvt_cvtsX2si_load" 9 (and (eq_attr "cpu" "athlon,k8") (and (eq_attr "type" "sseicvt") @@ -1045,7 +1045,7 @@ (and (eq_attr "mode" "SI,DI") (eq_attr "memory" "load"))))) "athlon-double,athlon-fploadk8,(athlon-fadd+athlon-fstore)") -;; cvtsd2si reg,reg is doublepath, troughput 1, latency 9 +;; cvtsd2si reg,reg is doublepath, throughput 1, latency 9 (define_insn_reservation "athlon_ssecvt_cvtsX2si" 9 (and (eq_attr "cpu" "athlon") (and (eq_attr "type" "sseicvt") @@ -1067,7 +1067,7 @@ (and (eq_attr "mode" "SI,DI") (eq_attr "memory" "none"))))) "athlon-double,athlon-fpsched,(athlon-fadd+athlon-fstore)") -;; cvtpd2dq reg,mem is doublepath, troughput 1, latency 9 on amdfam10 +;; cvtpd2dq reg,mem is doublepath, throughput 1, latency 9 on amdfam10 (define_insn_reservation "athlon_sseicvt_cvtpd2dq_load_amdfam10" 9 (and (eq_attr "cpu" "amdfam10") (and (eq_attr "type" "sseicvt") @@ -1075,7 +1075,7 @@ (and (eq_attr "mode" "TI") (eq_attr "memory" "load"))))) "athlon-double,athlon-fploadk8,(athlon-faddmul+athlon-fstore)") -;; cvtpd2dq reg,mem is doublepath, troughput 1, latency 7 on amdfam10 +;; cvtpd2dq reg,mem is doublepath, throughput 1, latency 7 on amdfam10 (define_insn_reservation "athlon_sseicvt_cvtpd2dq_amdfam10" 7 (and (eq_attr "cpu" "amdfam10") (and (eq_attr "type" "sseicvt") diff --git a/gcc/config/i386/avx512fintrin.h b/gcc/config/i386/avx512fintrin.h index 7fa7e43a31c0..af65dc69f35c 100644 --- a/gcc/config/i386/avx512fintrin.h +++ b/gcc/config/i386/avx512fintrin.h @@ -57,7 +57,7 @@ typedef enum /* These _mm{,256}_avx512* intrins are initially duplicated from their _mm{,256}_* forms from AVX2 or before. At that time, e need to add them to prevent target option mismatch when calling AVX512 intrins implemented - with these intrins under no-evex512 function attribute. Thess intrins will + with these intrins under no-evex512 function attribute. These intrins will still be here to avoid huge changes. All AVX512 intrins calling those AVX2 intrins or before have changed their calls to these AVX512 version. */ extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) diff --git a/gcc/config/i386/btver2.md b/gcc/config/i386/btver2.md index 93522d59c54e..1e890b51cc78 100644 --- a/gcc/config/i386/btver2.md +++ b/gcc/config/i386/btver2.md @@ -18,11 +18,11 @@ ;; AMD btver2 scheduling -;; Instructions decoded are that are classifed as direct (fast path single), +;; Instructions decoded are that are classified as direct (fast path single), ;; double (fast path double) and vector instructions. -;; Direct instrucions are decoded and convereted into 1 cop -;; Double instrucions are decoded and converetd into 2 cops -;; Vector instrucions are microcoded and they generated converted to +;; Direct instructions are decoded and converted into 1 cop +;; Double instructions are decoded and converted into 2 cops +;; Vector instructions are microcoded and they generated converted to ;; 3 or more cops. (define_attr "btver2_decode" "direct,vector,double" @@ -257,7 +257,7 @@ (eq_attr "memory" "store")))) "btver2-direct,btver2-alu,btver2-store") -;; Other integer instrucions +;; Other integer instructions (define_insn_reservation "btver2_idirect" 1 (and (eq_attr "cpu" "btver2") (and (eq_attr "btver2_decode" "direct") @@ -509,7 +509,7 @@ (eq_attr "type" "sse"))))) "btver2-double,btver2-load,btver2-fpm*42") -;; Bitmanipulation instrucions BMI LZCNT POPCNT +;; Bitmanipulation instructions BMI LZCNT POPCNT (define_insn_reservation "btver2_bmi_reg_direct" 1 (and (eq_attr "cpu" "btver2") (and (eq_attr "btver2_decode" "direct") diff --git a/gcc/config/i386/c86-4g-m7.md b/gcc/config/i386/c86-4g-m7.md index 96bd322a2883..73206a1678de 100644 --- a/gcc/config/i386/c86-4g-m7.md +++ b/gcc/config/i386/c86-4g-m7.md @@ -33,7 +33,7 @@ (define_cpu_unit "c86-4g-m7-decode3" "c86_4g_m7") ;; Currently blocking all decoders for vector path instructions as -;; they are dispatched separetely as microcode sequence. +;; they are dispatched separately as microcode sequence. (define_reservation "c86-4g-m7-vector" "c86-4g-m7-decode0+c86-4g-m7-decode1+c86-4g-m7-decode2+c86-4g-m7-decode3") ;; Direct instructions can be issued to any of the four decoders. @@ -222,7 +222,7 @@ (eq_attr "memory" "load")))) "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3,c86-4g-m7-idiv*6") -;; Integer/genaral Instructions +;; Integer/general Instructions (define_insn_reservation "c86_4g_m7_insn" 1 (and (eq_attr "cpu" "c86_4g_m7") (and (eq_attr "type" "alu,negnot,rotate1,ishift1,test,incdec,icmp, diff --git a/gcc/config/i386/c86-4g.md b/gcc/config/i386/c86-4g.md index 8b81fcaabb28..68aab28a2cfd 100644 --- a/gcc/config/i386/c86-4g.md +++ b/gcc/config/i386/c86-4g.md @@ -43,7 +43,7 @@ (define_cpu_unit "c86-4g-decode3" "c86_4g") ;; Currently blocking all decoders for vector path instructions as -;; they are dispatched separetely as microcode sequence. +;; they are dispatched separately as microcode sequence. ;; Fix me: Need to revisit this. (define_reservation "c86-4g-vector" "c86-4g-decode0+c86-4g-decode1+c86-4g-decode2+c86-4g-decode3") @@ -792,7 +792,7 @@ "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp1,c86-4g-fp1") ;; SSE moves -;; Fix me: Need to revist this again some of the moves may be restricted +;; Fix me: Need to revisit this again some of the moves may be restricted ;; to some fpu pipes. ;; movnt doesn't touch cache, so latency modeling has little impact. diff --git a/gcc/config/i386/cygwin.h b/gcc/config/i386/cygwin.h index 5460558cb1b6..0e915706f22b 100644 --- a/gcc/config/i386/cygwin.h +++ b/gcc/config/i386/cygwin.h @@ -107,10 +107,10 @@ along with GCC; see the file COPYING3. If not see #if defined (USE_CYGWIN_LIBSTDCXX_WRAPPERS) #if USE_CYGWIN_LIBSTDCXX_WRAPPERS -/* Default on, only explict -mno disables. */ +/* Default on, only explicit -mno disables. */ #define CXX_WRAP_SPEC_OPT "!mno-use-libstdc-wrappers" #else -/* Default off, only explict -m enables. */ +/* Default off, only explicit -m enables. */ #define CXX_WRAP_SPEC_OPT "muse-libstdc-wrappers" #endif diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc index bf686c359e5c..56938a822225 100644 --- a/gcc/config/i386/i386-c.cc +++ b/gcc/config/i386/i386-c.cc @@ -44,7 +44,7 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, void (*def_or_undef) (cpp_reader *, const char *)) { - /* For some of the k6/pentium varients there weren't separate ISA bits to + /* For some of the k6/pentium variants there weren't separate ISA bits to identify which tune/arch flag was passed, so figure it out here. */ size_t arch_len = strlen (ix86_arch_string); size_t tune_len = strlen (ix86_tune_string); diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index 6af5b7751b2c..f422f65fbc5a 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -2466,7 +2466,7 @@ ix86_expand_branch (enum rtx_code code, rtx op0, rtx op1, rtx label) machine_mode mode = GET_MODE (op0); rtx tmp; - /* Handle special case - vector comparsion with boolean result, transform + /* Handle special case - vector comparison with boolean result, transform it using ptest instruction or vpcmpeq + kortest. */ if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT || (mode == TImode && !TARGET_64BIT) @@ -4915,7 +4915,7 @@ ix86_expand_int_sse_cmp (rtx dest, enum rtx_code code, rtx cop0, rtx cop1, && GET_MODE_CLASS (mode) == MODE_VECTOR_INT && GET_MODE_SIZE (mode) <= 16) ; - /* AVX512F supports all of the comparsions + /* AVX512F supports all of the comparisons on all 128/256/512-bit vector int types. */ else if (ix86_use_mask_cmp_p (data_mode, mode, op_true, op_false)) ; @@ -5641,11 +5641,11 @@ ix86_expand_vec_perm (rtx operands[]) else emit_insn (gen_avx2_pshufbv32qi3 (t1, mask, vt)); - /* Multiply the shuffle indicies by two. */ + /* Multiply the shuffle indices by two. */ t1 = expand_simple_binop (maskmode, PLUS, t1, t1, t1, 1, OPTAB_DIRECT); - /* Add one to the odd shuffle indicies: + /* Add one to the odd shuffle indices: t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */ for (i = 0; i < w / 2; ++i) { @@ -8812,7 +8812,7 @@ expand_small_cpymem_or_setmem (rtx destmem, rtx srcmem, } /* Handle small memcpy (up to SIZE that is supposed to be small power of 2. - and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN + and get ready for the main memcpy loop by copying initial DESIRED_ALIGN-ALIGN bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can proceed with an loop copying SIZE bytes at once. Do moves in MODE. DONE_LABEL is a label after the whole copying sequence. The label is created @@ -9521,7 +9521,7 @@ ix86_copy_addr_to_reg (rtx addr) 1) missaligned move prologue/epilogue containing: a) Prologue handling small memory blocks and jumping to done_label (skipped if blocks are known to be large enough) - b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is + b) Single move copying first DESIRED_ALIGN-ALIGN bytes if alignment is needed by single possibly misaligned move (skipped if alignment is not needed) c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves @@ -14469,7 +14469,7 @@ ix86_expand_special_args_builtin (const struct builtin_description *d, op = fixup_modeless_constant (op, mode); /* NB: 3-operands load implied it's a mask load or v{p}expand*, - and that mask operand shoud be at the end. + and that mask operand should be at the end. Keep all-ones mask which would be simplified by the expander. */ if (nargs == 3 && i == 2 && klass == load && constm1_operand (op, mode) @@ -18395,7 +18395,7 @@ ix86_expand_vector_init_interleave (machine_mode mode, } else { - /* Extend the odd elment to SImode using a paradoxical SUBREG. */ + /* Extend the odd element to SImode using a paradoxical SUBREG. */ op0 = gen_reg_rtx (SImode); emit_move_insn (op0, gen_lowpart (SImode, op)); @@ -18408,7 +18408,7 @@ ix86_expand_vector_init_interleave (machine_mode mode, const1_rtx); emit_insn (gen_rtx_SET (op1, op0)); - /* Cast the V4SImode vector back to a vector in orignal mode. */ + /* Cast the V4SImode vector back to a vector in original mode. */ op0 = gen_reg_rtx (mode); emit_move_insn (op0, gen_lowpart (mode, op1)); @@ -22529,7 +22529,7 @@ expand_vec_perm_shufps_shufps (struct expand_vec_perm_d *d) perm1[3] = perm1[2] = (count == 3) ? d->perm[pair_idx] : d->perm[pair_idx] + 4; - /* Alway put the vector contains lone indx at the first. */ + /* Always put the vector contains lone indx at the first. */ if (count == 1) std::swap (d->op0, d->op1); @@ -26551,7 +26551,7 @@ ix86_expand_sse2_mulvxdi3 (rtx op0, rtx op1, rtx op2) gen_rtx_MULT (mode, op1, op2)); } -/* Return 1 if control tansfer instruction INSN +/* Return 1 if control transfer instruction INSN should be encoded with notrack prefix. */ bool @@ -27139,7 +27139,7 @@ ix86_gen_ccmp_first (rtx_insn **prep_seq, rtx_insn **gen_seq, /* We only supports following scalar comparisons that use just 1 instruction: DI/SI/QI/HI/DF/SF/HF. - Unordered/Ordered compare cannot be corretly indentified by + Unordered/Ordered compare cannot be correctly identified by ccmp so they are not supported. */ if (!(op_mode == DImode || op_mode == SImode || op_mode == HImode || op_mode == QImode || op_mode == DFmode || op_mode == SFmode diff --git a/gcc/config/i386/i386-features.cc b/gcc/config/i386/i386-features.cc index 0694811e9da9..68d76d364ccb 100644 --- a/gcc/config/i386/i386-features.cc +++ b/gcc/config/i386/i386-features.cc @@ -2478,7 +2478,7 @@ general_scalar_to_vector_candidate_p (rtx_insn *insn, enum machine_mode mode) return REG_P (dst); case VEC_SELECT: - /* Excluding MEM_P (dst) avoids intefering with vpextr[dq]. */ + /* Excluding MEM_P (dst) avoids interfering with vpextr[dq]. */ return REG_P (dst) && REG_P (XEXP (src, 0)) && GET_MODE (XEXP (src, 0)) == (mode == DImode ? V2DImode @@ -4879,7 +4879,7 @@ pass_x86_cse::x86_cse (void) continue; bool matched = false; - /* Remove redundant pattens if there are more than 2 of + /* Remove redundant patterns if there are more than 2 of them. */ unsigned int threshold = 2; @@ -5302,14 +5302,14 @@ ix86_apx_nf_convert (void) continue; /* Convert candidate insns after cstore, which should - satisify the two conditions: + satisfy the two conditions: 1. Is not flag user or producer, only clobbers FLAGS_REG. 2. Have corresponding nf pattern. */ rtx pat = PATTERN (insn); - /* Starting convertion at first cstorecc. */ + /* Starting conversion at first cstorecc. */ rtx set = NULL_RTX; if (!converting_seq && (set = single_set (insn)) @@ -5819,7 +5819,7 @@ dispatch_function_versions (tree dispatch_decl, gseq = bb_seq (*empty_bb); /* Function version dispatch is via IFUNC. IFUNC resolvers fire before - constructors, so explicity call __builtin_cpu_init here. */ + constructors, so explicitly call __builtin_cpu_init here. */ ifunc_cpu_init_stmt = gimple_build_call_vec (get_ix86_builtin (IX86_BUILTIN_CPU_INIT), vNULL); gimple_seq_add_stmt (&gseq, ifunc_cpu_init_stmt); diff --git a/gcc/config/i386/i386-features.h b/gcc/config/i386/i386-features.h index e999444a8773..febcf62e72d1 100644 --- a/gcc/config/i386/i386-features.h +++ b/gcc/config/i386/i386-features.h @@ -145,7 +145,7 @@ class scalar_chain bitmap insns; /* All registers defined by a chain. */ bitmap defs; - /* Registers used in both vector and sclar modes. */ + /* Registers used in both vector and scalar modes. */ bitmap defs_conv; /* Limit on chain discovery. */ diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index 7ffe9cd2a38c..9e0e36351e73 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -878,7 +878,7 @@ ix86_function_specific_restore (struct gcc_options *opts, opts->x_ix86_tune_memset_strategy = ptr->x_ix86_tune_memset_strategy; opts->x_ix86_tune_no_default = ptr->x_ix86_tune_no_default; ix86_tune_cost = processor_cost_table[ix86_tune]; - /* TODO: ix86_cost should be chosen at instruction or function granuality + /* TODO: ix86_cost should be chosen at instruction or function granularity so for cold code we use size_cost even in !optimize_size compilation. */ if (opts->x_optimize_size) ix86_cost = &ix86_size_cost; @@ -1454,7 +1454,7 @@ ix86_valid_target_attribute_tree (tree fndecl, tree args, opts->x_ix86_tune_string = ggc_strdup (option_strings[IX86_FUNCTION_SPECIFIC_TUNE]); /* If we have explicit arch string and no tune string specified, set - tune_string to NULL and later it will be overriden by arch_string + tune_string to NULL and later it will be overridden by arch_string so target clones can get proper optimization. */ else if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH] || orig_tune_defaulted) @@ -1959,7 +1959,7 @@ ix86_override_options_after_change_1 (struct gcc_options *opts, OPTS (flag_web) = OPTS (flag_unroll_loops); if (!OPTS_SET_P (flag_rename_registers)) OPTS (flag_rename_registers) = OPTS (flag_unroll_loops); - /* -fcunroll-grow-size default follws -f[no]-unroll-loops. */ + /* -fcunroll-grow-size default follows -f[no]-unroll-loops. */ if (!OPTS_SET_P (flag_cunroll_grow_size)) OPTS (flag_cunroll_grow_size) = (OPTS (flag_unroll_loops) @@ -2532,7 +2532,7 @@ ix86_option_override_internal (bool main_args_p, ix86_override_options_after_change_1 (opts, opts_set); ix86_tune_cost = processor_cost_table[ix86_tune]; - /* TODO: ix86_cost should be chosen at instruction or function granuality + /* TODO: ix86_cost should be chosen at instruction or function granularity so for cold code we use size_cost even in !optimize_size compilation. */ if (opts->x_optimize_size) ix86_cost = &ix86_size_cost; diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index 9148ac1e0571..22980411180e 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -235,7 +235,7 @@ unsigned int const debugger64_register_map[FIRST_PSEUDO_REGISTER] = 75, 76, 77, 78, 79, 80, 81, 82, /* Mask registers */ 118, 119, 120, 121, 122, 123, 124, 125, - /* rex2 extend interger registers */ + /* rex2 extend integer registers */ 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145 }; @@ -685,7 +685,7 @@ ix86_can_inline_p (tree caller, tree callee) ret = false; else if (caller_opts->x_ix86_fpmath != callee_opts->x_ix86_fpmath - /* If the calle doesn't use FP expressions differences in + /* If the callee doesn't use FP expressions differences in ix86_fpmath can be ignored. We are called from FEs for multi-versioning call optimization, so beware of ipa_fn_summaries not available. */ @@ -1321,7 +1321,7 @@ ix86_function_regparm (const_tree type, const_tree decl) /* Each fixed register usage increases register pressure, so less registers should be used for argument passing. - This functionality can be overriden by an explicit + This functionality can be overridden by an explicit regparm value. */ for (regno = AX_REG; regno <= DI_REG; regno++) if (fixed_regs[regno]) @@ -1344,7 +1344,7 @@ ix86_function_regparm (const_tree type, const_tree decl) indicated TYPE and DECL. DECL may be NULL when calling function indirectly or considering a libcall. Return -1 if any FP parameter should be rejected by error. This is used in siutation we imply SSE - calling convetion but the function is called from another function with + calling convention but the function is called from another function with SSE disabled. Otherwise return 0. */ static int @@ -3076,7 +3076,7 @@ construct_container (machine_mode mode, machine_mode orig_mode, and data type TYPE. (TYPE is null for libcalls where that information may not be available.) - Return a number of integer regsiters advanced over. */ + Return a number of integer registers advanced over. */ static int function_arg_advance_32 (CUMULATIVE_ARGS *cum, machine_mode mode, @@ -4521,7 +4521,7 @@ ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) if (size < 8) return false; - /* Unless ABI prescibes otherwise, + /* Unless ABI prescribes otherwise, MMX/3dNow values are returned in MM0 if available. */ if (size == 8) @@ -6356,7 +6356,7 @@ output_indirect_thunk (unsigned int regno) fputs ("\tint3\n", asm_out_file); } -/* Output a funtion with a call and return thunk for indirect branch. +/* Output a function with a call and return thunk for indirect branch. If REGNO != INVALID_REGNUM, the function address is in REGNO. Otherwise, the function address is on the top of stack. Thunk is used for function return if RET_P is true. */ @@ -7088,8 +7088,8 @@ ix86_compute_frame_layout (void) frame->nsseregs = ix86_nsaved_sseregs (); /* 64-bit MS ABI seem to require stack alignment to be always 16, - except for function prologues, leaf functions and when the defult - incoming stack boundary is overriden at command line or via + except for function prologues, leaf functions and when the default + incoming stack boundary is overridden at command line or via force_align_arg_pointer attribute. Darwin's ABI specifies 128b alignment for both 32 and 64 bit variants @@ -7118,7 +7118,7 @@ ix86_compute_frame_layout (void) gcc_assert (preferred_alignment <= stack_alignment_needed); /* The only ABI saving SSE regs should be 64-bit ms_abi or with - no_caller_saved_registers attribue. */ + no_caller_saved_registers attribute. */ gcc_assert (TARGET_64BIT || (cfun->machine->call_saved_registers == TYPE_NO_CALLER_SAVED_REGISTERS) @@ -7564,7 +7564,7 @@ choose_basereg (HOST_WIDE_INT cfa_offset, rtx &base_reg, /* Return an RTX that points to CFA_OFFSET within the stack frame and the alignment of address. If ALIGN is non-null, it should point to an alignment value (in bits) that is preferred or zero and will - recieve the alignment of the base register that was selected, + receive the alignment of the base register that was selected, irrespective of rather or not CFA_OFFSET is a multiple of that alignment value. If it is possible for the base register offset to be non-immediate then SCRATCH_REGNO should specify a scratch register to @@ -7714,7 +7714,7 @@ ix86_emit_save_reg_using_mov (machine_mode mode, unsigned int regno, addr = choose_baseaddr (cfa_offset, &align); mem = gen_frame_mem (mode, addr); - /* The location aligment depends upon the base register. */ + /* The location alignment depends upon the base register. */ align = MIN (GET_MODE_ALIGNMENT (mode), align); gcc_assert (! (cfa_offset & (align / BITS_PER_UNIT - 1))); set_mem_align (mem, align); @@ -7951,7 +7951,7 @@ pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, } /* Find an available register to be used as dynamic realign argument - pointer regsiter. Such a register will be written in prologue and + pointer register. Such a register will be written in prologue and used in begin of body, so it must not be 1. parameter passing register. 2. GOT pointer. @@ -9813,7 +9813,7 @@ ix86_expand_prologue (void) } gcc_assert (m->fs.sp_offset == frame.stack_pointer_offset); - /* If we havn't already set up the frame pointer, do so now. */ + /* If we haven't already set up the frame pointer, do so now. */ if (frame_pointer_needed && !m->fs.fp_valid) { insn = gen_add3_insn (hard_frame_pointer_rtx, stack_pointer_rtx, @@ -9845,7 +9845,7 @@ ix86_expand_prologue (void) RTX_FRAME_RELATED_P (insn) = 1; add_reg_note (insn, REG_CFA_FLUSH_QUEUE, NULL_RTX); emit_insn (gen_prologue_use (pic)); - /* Deleting already emmitted SET_GOT if exist and allocated to + /* Deleting already emitted SET_GOT if exist and allocated to REAL_PIC_OFFSET_TABLE_REGNUM. */ ix86_elim_entry_set_got (pic); } @@ -10160,7 +10160,7 @@ ix86_emit_restore_sse_regs_using_mov (HOST_WIDE_INT cfa_offset, mem = choose_baseaddr (cfa_offset, &align); mem = gen_rtx_MEM (V4SFmode, mem); - /* The location aligment depends upon the base register. */ + /* The location alignment depends upon the base register. */ align = MIN (GET_MODE_ALIGNMENT (V4SFmode), align); gcc_assert (! (cfa_offset & (align / BITS_PER_UNIT - 1))); set_mem_align (mem, align); @@ -12104,7 +12104,7 @@ ix86_memory_address_reg_class (rtx_insn* insn) /* Update recog_data for processing of alternatives. */ extract_insn_cached (insn); - /* If current alternative is not set, loop throught enabled + /* If current alternative is not set, loop through enabled alternatives and get the most limited register class. */ if (saved_alternative == -1) { @@ -12347,7 +12347,7 @@ ix86_legitimate_address_p (machine_mode, rtx addr, bool strict, #if TARGET_MACHO else if (MACHO_DYNAMIC_NO_PIC_P && !ix86_legitimate_constant_p (Pmode, disp)) - /* displacment must be referenced via non_lazy_pointer */ + /* displacement must be referenced via non_lazy_pointer */ return false; #endif @@ -15760,7 +15760,7 @@ ix86_avx_u128_mode_after (int mode, rtx_insn *insn) if (avx_upper_reg_found) return AVX_U128_DIRTY; - /* If the function desn't clobber any sse registers or only clobber + /* If the function doesn't clobber any sse registers or only clobber 128-bit part, Then vzeroupper isn't issued before the function exit. the status not CLEAN but ANY after the function. */ const function_abi &abi = insn_callee_abi (insn); @@ -16167,7 +16167,7 @@ ix86_output_addr_diff_elt (FILE *file, int value, int rel) /* Increase given DISTANCE in half-cycles according to dependencies between PREV and NEXT instructions. Add 1 half-cycle if there is no dependency and - go to next cycle if there is some dependecy. */ + go to next cycle if there is some dependency. */ static unsigned int increase_distance (rtx_insn *prev, rtx_insn *next, unsigned int distance) @@ -16534,7 +16534,7 @@ ix86_lea_outperforms (rtx_insn *insn, unsigned int regno0, unsigned int regno1, lea priority. */ dist_define += split_cost + IX86_LEA_PRIORITY; - /* If there is no use in memory addess then we just check + /* If there is no use in memory address then we just check that split cost exceeds AGU stall. */ if (dist_use < 0) return dist_define > LEA_MAX_STALL; @@ -16660,7 +16660,7 @@ ix86_avoid_lea_for_addr (rtx_insn *insn, rtx operands[]) if split lea into a sequence of instructions. */ if (parts.base || parts.index) { - /* Have to use mov instruction if non desctructive + /* Have to use mov instruction if non destructive destination form is used. */ if (regno1 != regno0 && regno2 != regno0) split_cost += 1; @@ -17272,7 +17272,7 @@ ix86_cc_modes_compatible (machine_mode m1, machine_mode m2) } /* Return strategy to use for floating-point. We assume that fcomi is always - preferrable where available, since that is also true when looking at size + preferable where available, since that is also true when looking at size (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */ enum ix86_fpcmp_strategy @@ -18310,7 +18310,7 @@ add_parameter_dependencies (rtx_insn *call, rtx_insn *head) } if (insn_is_function_arg (insn, &is_spilled)) { - /* Add output depdendence between two function arguments if chain + /* Add output dependence between two function arguments if chain of output arguments contains likely spilled HW registers. */ if (is_spilled) add_dependence (first_arg, insn, REG_DEP_OUTPUT); @@ -18713,7 +18713,7 @@ ix86_data_alignment (tree type, unsigned int align, bool opt) return align; } -/* Implememnt TARGET_LOWER_LOCAL_DECL_ALIGNMENT. */ +/* Implement TARGET_LOWER_LOCAL_DECL_ALIGNMENT. */ static void ix86_lower_local_decl_alignment (tree decl) { @@ -20210,7 +20210,7 @@ ix86_gimple_fold_builtin (gimple_stmt_iterator *gsi) { unsigned sel_idx; /* Imm[1:0](if VL > 128, then use Imm[3:2],Imm[5:4],Imm[7:6]) - provide 2 select constrols for each element of the + provide 2 select controls for each element of the destination. */ if (imode == E_DFmode) sel_idx = (i & 1) * elems + (i & ~1) @@ -26023,7 +26023,7 @@ ix86_autovectorize_vector_modes (vector_modes *modes, bool all) return ix86_vect_compare_costs ? VECT_COMPARE_COSTS : 0; } -/* Implemenation of targetm.vectorize.get_mask_mode. */ +/* Implementation of targetm.vectorize.get_mask_mode. */ static opt_machine_mode ix86_get_mask_mode (machine_mode data_mode) @@ -26097,7 +26097,7 @@ ix86_max_noce_ifcvt_seq_cost (edge e) /* For modern machines with deeper pipeline, the penalty for branch misprediction could be higher than before to reset the pipeline slots. Add parameter br_mispredict_scale as a factor to describe - the impact of reseting the pipeline. */ + the impact of resetting the pipeline. */ return BRANCH_COST (true, predictable_p) * ix86_tune_cost->br_mispredict_scale; @@ -26363,7 +26363,7 @@ ix86_vector_costs::add_stmt_cost (int count, vect_cost_for_stmt kind, p = a < b c = p ? x : y and we will account first statement as setcc. Exception is when - p is loaded from memory as bool and then we will not acocunt + p is loaded from memory as bool and then we will not account the compare, but there is no way to check for this. */ int ninsns = TARGET_SSE4_1 ? 1 : 3; @@ -26883,7 +26883,7 @@ ix86_vector_costs::finish_cost (const vector_costs *scalar_costs) { /* We are currently not asking the vectorizer to compare costs between different vector mode sizes. When using predication - that will end up always choosing the prefered mode size even + that will end up always choosing the preferred mode size even if there's a smaller mode covering all lanes. Test for this situation and artificially reject the larger mode attempt. ??? We currently lack masked ops for sub-SSE sized modes, @@ -27711,7 +27711,7 @@ ix86_optab_supported_p (int op, machine_mode mode1, machine_mode, to use %fs and %gs segment prefixes. Therefore: (a) All address spaces have the same modes, - (b) All address spaces have the same addresss forms, + (b) All address spaces have the same address forms, (c) While %fs and %gs are technically subsets of the generic address space, they are probably not subsets of each other. (d) Since we have no access to the segment base register values @@ -27863,7 +27863,7 @@ ix86_push_rounding (poly_int64 bytes) } /* Use 8 bits metadata start from bit48 for LAM_U48, - 6 bits metadat start from bit57 for LAM_U57. */ + 6 bits metadata start from bit57 for LAM_U57. */ #define IX86_HWASAN_SHIFT (ix86_lam_type == lam_u48 \ ? 48 \ : (ix86_lam_type == lam_u57 ? 57 : 0)) diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index ca71a345794c..c4befa06ba6b 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -794,7 +794,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); /* 1 if -mstackrealign should be turned on by default. It will generate an alternate prologue and epilogue that realigns the - runtime stack if nessary. This supports mixing codes that keep a + runtime stack if necessary. This supports mixing codes that keep a 4-byte aligned stack, as specified by i386 psABI, with codes that need a 16-byte aligned stack, as required by SSE instructions. */ #define STACK_REALIGN_DEFAULT 0 @@ -805,7 +805,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); /* According to Windows x64 software convention, the maximum stack allocatable in the prologue is 4G - 8 bytes. Furthermore, there is a limited set of instructions allowed to adjust the stack pointer in the epilog, forcing the - use of frame pointer for frames larger than 2 GB. This theorical limit + use of frame pointer for frames larger than 2 GB. This theoretical limit is reduced by 256, an over-estimated upper bound for the stack use by the prologue. We define only one threshold for both the prolog and the epilog. When the @@ -1631,7 +1631,7 @@ enum reg_class FIXME: Unlike earlier implementations, the size of unwind info seems to actually grow with accumulation. Is that because accumulated args - unwind info became unnecesarily bloated? + unwind info became unnecessarily bloated? With the 64-bit MS ABI, we can generate correct code with or without accumulated args, but because of OUTGOING_REG_PARM_STACK_SPACE the code diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index b4f1bf4b5cd2..0fdf99416e69 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -193,7 +193,7 @@ ;; For CRC32 support UNSPEC_CRC32 - ;; For LZCNT suppoprt + ;; For LZCNT support UNSPEC_LZCNT ;; For BMI support @@ -380,7 +380,7 @@ (ROUND_NO_EXC 0x8) ]) -;; Constants to represent AVX512F embeded rounding +;; Constants to represent AVX512F embedded rounding (define_constants [(ROUND_NEAREST_INT 0) (ROUND_NEG_INF 1) @@ -1910,7 +1910,7 @@ DONE; }) -;; For conditonal compare, the middle-end hook will convert +;; For conditional compare, the middle-end hook will convert ;; CCmode to sub-CCmode using SELECT_CC_MODE macro and try ;; to find cstore<submodes> in optab. Add ALL_CC to support ;; the cstore after ccmp sequence. @@ -10848,7 +10848,7 @@ (symbol_ref "true")))]) ;; x == 0 with zero flag test can be done also as x < 1U with carry flag -;; test, where the latter is preferrable if we have some carry consuming +;; test, where the latter is preferable if we have some carry consuming ;; instruction. ;; For x != 0, we need to use x < 1U with negation of carry, i.e. ;; + (1 - CF). diff --git a/gcc/config/i386/i386elf.h b/gcc/config/i386/i386elf.h index a81ab08825f2..ca6a229b048e 100644 --- a/gcc/config/i386/i386elf.h +++ b/gcc/config/i386/i386elf.h @@ -20,7 +20,7 @@ along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ /* Define DEFAULT_PCC_STRUCT_RETURN to 1 because the i386 SVR4 ABI returns - records and unions in memory. ix86_option_override_internal will overide + records and unions in memory. ix86_option_override_internal will override this flag when compiling 64-bit code as we never do pcc_struct_return scheme on x86-64. */ #undef DEFAULT_PCC_STRUCT_RETURN diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index cf3a68a9fe85..998a3eeac41a 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -901,7 +901,7 @@ return i == 3 || i == 5 || i == 9; }) -;; Match 4 or 8 to 11. Used for embeded rounding. +;; Match 4 or 8 to 11. Used for embedded rounding. (define_predicate "const_4_or_8_to_11_operand" (match_code "const_int") { @@ -1928,7 +1928,7 @@ return true; }) -;; Return true if OP is a constant pool in perm{w,d,b} which constains index +;; Return true if OP is a constant pool in perm{w,d,b} which contains index ;; match pmov{dw,wb,qd}. (define_predicate "permvar_truncate_operand" (match_code "mem") @@ -1958,7 +1958,7 @@ return true; }) -;; Return true if OP is a constant pool in shufb which constains index +;; Return true if OP is a constant pool in shufb which contains index ;; match pmovdw. (define_predicate "pshufb_truncv4siv4hi_operand" (match_code "mem") @@ -1988,7 +1988,7 @@ return true; }) -;; Return true if OP is a constant pool in shufb which constains index +;; Return true if OP is a constant pool in shufb which contains index ;; match pmovdw. (define_predicate "pshufb_truncv8hiv8qi_operand" (match_code "mem") diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index d48e2380c228..21773384973f 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -175,7 +175,7 @@ ;; For AVX512BF16 support UNSPEC_VDPBF16PS - ;; For AVX512FP16 suppport + ;; For AVX512FP16 support UNSPEC_COMPLEX_FMA UNSPEC_COMPLEX_FMA_PAIR UNSPEC_COMPLEX_FCMA @@ -214,7 +214,7 @@ UNSPEC_SM4KEY4 UNSPEC_SM4RNDS4 - ;; For AVX10.2 suppport + ;; For AVX10.2 support UNSPEC_VDPPHPS UNSPEC_VCVTBIASPH2BF8 UNSPEC_VCVTBIASPH2BF8S @@ -256,7 +256,7 @@ UNSPEC_VBMACXOR UNSPEC_VBITREV - ;; For MOVRS suppport + ;; For MOVRS support UNSPEC_VMOVRS ]) @@ -14042,7 +14042,7 @@ UNSPEC_VTERNLOG))] "(<MODE_SIZE> == 64 || TARGET_AVX512VL || (TARGET_AVX512F && !TARGET_PREFER_AVX256)) -/* Disallow embeded broadcast for vector HFmode since +/* Disallow embedded broadcast for vector HFmode since it's not real AVX512FP16 instruction. */ && (GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) >= 4 || GET_CODE (operands[3]) != VEC_DUPLICATE)" @@ -17807,7 +17807,7 @@ (const_string "0"))) (set_attr "mode" "<sseinsnmode>")]) -;; PR target/101796: Transfrom movl+vpbranchcastw+vpsravw to vpsraw +;; PR target/101796: Transform movl+vpbranchcastw+vpsravw to vpsraw ;; when COUNT is immediate. (define_split [(set (match_operand:VI248_AVX512BW 0 "register_operand") diff --git a/gcc/config/i386/x86-tune-costs.h b/gcc/config/i386/x86-tune-costs.h index 7819fdf7c021..deb752889acc 100644 --- a/gcc/config/i386/x86-tune-costs.h +++ b/gcc/config/i386/x86-tune-costs.h @@ -1616,7 +1616,7 @@ struct processor_costs znver1_cost = { /* Start of register allocator costs. integer->integer move cost is 2. */ /* reg-reg moves are done by renaming and thus they are even cheaper than - 1 cycle. Becuase reg-reg move cost is 2 and the following tables correspond + 1 cycle. Because reg-reg move cost is 2 and the following tables correspond to doubles of latencies, we do not model this correctly. It does not seem to make practical difference to bump prices up even more. */ 6, /* cost for loading QImode using @@ -2355,13 +2355,13 @@ struct processor_costs znver5_cost = { /* FMA had throughput 2 and latency 4. */ COSTS_N_INSNS (4), /* cost of FMA SS instruction. */ COSTS_N_INSNS (4), /* cost of FMA SD instruction. */ - /* DIVSS has throughtput 0.4 and latency 10. */ + /* DIVSS has throughput 0.4 and latency 10. */ COSTS_N_INSNS (10), /* cost of DIVSS instruction. */ - /* DIVSD has throughtput 0.25 and latency 13. */ + /* DIVSD has throughput 0.25 and latency 13. */ COSTS_N_INSNS (13), /* cost of DIVSD instruction. */ - /* DIVSD has throughtput 0.22 and latency 14. */ + /* DIVSD has throughput 0.22 and latency 14. */ COSTS_N_INSNS (14), /* cost of SQRTSS instruction. */ - /* DIVSD has throughtput 0.13 and latency 20. */ + /* DIVSD has throughput 0.13 and latency 20. */ COSTS_N_INSNS (20), /* cost of SQRTSD instruction. */ COSTS_N_INSNS (3), /* cost of CVTSS2SD etc. */ COSTS_N_INSNS (5), /* cost of 256bit VCVTPS2PD etc. */ @@ -2378,7 +2378,7 @@ struct processor_costs znver5_cost = { for register pressure. - fp ops: 2 additions per cycle, latency 2-3 2 multiplicaitons per cycle, latency 3 - - vector intger ops: 4 additions, latency 1 + - vector integer ops: 4 additions, latency 1 2 multiplications, latency 4 We increase width to 6 for multiplications in ix86_reassociation_width. */ @@ -2402,7 +2402,7 @@ struct processor_costs znver5_cost = { COSTS_N_INSNS (2), /* Branch mispredict scale. */ }; -/* skylake_cost should produce code tuned for Skylake familly of CPUs. */ +/* skylake_cost should produce code tuned for Skylake family of CPUs. */ static stringop_algs skylake_memcpy[2] = { {libcall, {{256, rep_prefix_1_byte, true}, @@ -4277,7 +4277,7 @@ struct processor_costs generic_cost = { COSTS_N_INSNS (2), /* Branch mispredict scale. */ }; -/* core_cost should produce code tuned for Core familly of CPUs. */ +/* core_cost should produce code tuned for Core family of CPUs. */ static stringop_algs core_memcpy[2] = { {libcall, {{1024, rep_prefix_4_byte, true}, {-1, libcall, false}}}, {libcall, {{24, loop, true}, {128, rep_prefix_8_byte, true}, diff --git a/gcc/config/i386/x86-tune-sched-atom.cc b/gcc/config/i386/x86-tune-sched-atom.cc index 279623aac07f..da2ac1b4cb1d 100644 --- a/gcc/config/i386/x86-tune-sched-atom.cc +++ b/gcc/config/i386/x86-tune-sched-atom.cc @@ -188,7 +188,7 @@ swap_top_of_ready_list (rtx_insn **ready, int n_ready) #undef INSN_TICK } -/* Perform possible reodering of ready list for Atom/Silvermont only. +/* Perform possible reordering of ready list for Atom/Silvermont only. Return issue rate. */ int ix86_atom_sched_reorder (FILE *dump, int sched_verbose, rtx_insn **ready, @@ -203,7 +203,7 @@ ix86_atom_sched_reorder (FILE *dump, int sched_verbose, rtx_insn **ready, /* Set up issue rate. */ issue_rate = ix86_issue_rate (); - /* Do reodering for BONNELL/SILVERMONT only. */ + /* Do reordering for BONNELL/SILVERMONT only. */ if (!TARGET_CPU_P (BONNELL) && !TARGET_CPU_P (SILVERMONT) && !TARGET_CPU_P (INTEL)) return issue_rate; @@ -212,7 +212,7 @@ ix86_atom_sched_reorder (FILE *dump, int sched_verbose, rtx_insn **ready, if (n_ready <= 1) return issue_rate; - /* Do reodering for post-reload scheduler only. */ + /* Do reordering for post-reload scheduler only. */ if (!reload_completed) return issue_rate; diff --git a/gcc/config/i386/x86-tune-sched-bd.cc b/gcc/config/i386/x86-tune-sched-bd.cc index 5602478f2351..ade6f45a55c8 100644 --- a/gcc/config/i386/x86-tune-sched-bd.cc +++ b/gcc/config/i386/x86-tune-sched-bd.cc @@ -143,7 +143,7 @@ typedef struct dispatch_windows_s { struct dispatch_windows_s *prev; } dispatch_windows; -/* Immediate valuse used in an insn. */ +/* Immediate values used in an insn. */ typedef struct imm_info_s { int imm; @@ -372,7 +372,7 @@ find_constant (rtx in_rtx, imm_info *imm_values) /* Return total size of immediate operands of an instruction along with number of corresponding immediate-operands. It initializes its parameters to zero - befor calling FIND_CONSTANT. + before calling FIND_CONSTANT. INSN is the input instruction. IMM is the total of immediates. IMM32 is the number of 32 bit immediates. IMM64 is the number of 64 bit immediates. */ diff --git a/gcc/config/i386/x86-tune-sched.cc b/gcc/config/i386/x86-tune-sched.cc index 4fc955a12a5a..d6ef4e720edf 100644 --- a/gcc/config/i386/x86-tune-sched.cc +++ b/gcc/config/i386/x86-tune-sched.cc @@ -274,7 +274,7 @@ exact_store_load_dependency (rtx_insn *store, rtx_insn *load) between INSN and DEP_INSN through a dependence of type DEP_TYPE, and strength DW. It should return the new value. - On x86 CPUs this is most commonly used to model the fact that valus of + On x86 CPUs this is most commonly used to model the fact that values of registers used to compute address of memory operand needs to be ready earlier than values of registers used in the actual operation. */ diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def index 569398836e88..5b208dc7372a 100644 --- a/gcc/config/i386/x86-tune.def +++ b/gcc/config/i386/x86-tune.def @@ -159,7 +159,7 @@ DEF_TUNE (X86_TUNE_FUSE_MOV_AND_ALU, "fuse_mov_and_alu", /* X86_TUNE_FUSE_AND_BRANCH_MEM: Fuse alu with a subsequent conditional jump instruction when alu contains memory operand. - TODO: Not suported by TIGERLAKE and COPERLAKE, so m_CORE_AVX2 is wrong. */ + TODO: Not supported by TIGERLAKE and COOPERLAKE, so m_CORE_AVX2 is wrong. */ DEF_TUNE (X86_TUNE_FUSE_ALU_AND_BRANCH_MEM, "fuse_alu_and_branch_mem", m_SANDYBRIDGE | m_CORE_AVX2 | m_ZHAOXIN | m_GENERIC | m_ZNVER3 | m_ZNVER4 | m_ZNVER5) @@ -337,7 +337,7 @@ DEF_TUNE (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB, compact prologues and epilogues by issuing a misaligned moves. This requires target to handle misaligned moves and partial memory stalls reasonably well. - FIXME: This may actualy be a win on more targets than listed here. */ + FIXME: This may actually be a win on more targets than listed here. */ DEF_TUNE (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES, "misaligned_move_string_pro_epilogues", m_386 | m_486 | m_CORE_ALL | m_AMD_MULTIPLE | m_ZHAOXIN | m_TREMONT @@ -679,7 +679,7 @@ DEF_TUNE (X86_TUNE_DOUBLE_WITH_ADD, "double_with_add", ~m_386) /* X86_TUNE_ALWAYS_FANCY_MATH_387: controls use of fancy 387 operations, such as fsqrt, fprem, fsin, fcos, fsincos etc. - Should be enabled for all targets that always has coprocesor. */ + Should be enabled for all targets that always has coprocessor. */ DEF_TUNE (X86_TUNE_ALWAYS_FANCY_MATH_387, "always_fancy_math_387", ~(m_386 | m_486 | m_LAKEMONT)) @@ -743,7 +743,7 @@ DEF_TUNE (X86_TUNE_PARTIAL_MEMORY_READ_STALL, "partial_memory_read_stall", DEF_TUNE (X86_TUNE_PROMOTE_QIMODE, "promote_qimode", ~m_PPRO) -/* X86_TUNE_PROMOTE_HI_REGS: Same, but for 16bit artihmetic. Again we avoid +/* X86_TUNE_PROMOTE_HI_REGS: Same, but for 16bit arithmetic. Again we avoid partial register stalls on PentiumPro targets. */ DEF_TUNE (X86_TUNE_PROMOTE_HI_REGS, "promote_hi_regs", m_PPRO) diff --git a/gcc/config/i386/zn4zn5.md b/gcc/config/i386/zn4zn5.md index c6e96a107f80..99f0fb58b696 100644 --- a/gcc/config/i386/zn4zn5.md +++ b/gcc/config/i386/zn4zn5.md @@ -34,7 +34,7 @@ (define_cpu_unit "znver4-decode3" "znver4") ;; Currently blocking all decoders for vector path instructions as -;; they are dispatched separetely as microcode sequence. +;; they are dispatched separately as microcode sequence. (define_reservation "znver4-vector" "znver4-decode0+znver4-decode1+znver4-decode2+znver4-decode3") ;; Direct instructions can be issued to any of the four decoders. diff --git a/gcc/config/i386/znver.md b/gcc/config/i386/znver.md index f5a080dfd0c0..84ebbbfd6351 100644 --- a/gcc/config/i386/znver.md +++ b/gcc/config/i386/znver.md @@ -34,7 +34,7 @@ (define_cpu_unit "znver1-decode3" "znver1") ;; Currently blocking all decoders for vector path instructions as -;; they are dispatched separetely as microcode sequence. +;; they are dispatched separately as microcode sequence. ;; Fix me: Need to revisit this. (define_reservation "znver1-vector" "znver1-decode0+znver1-decode1+znver1-decode2+znver1-decode3") @@ -478,7 +478,7 @@ (eq_attr "type" "lea")) "znver1-direct,znver1-ieu") -;; Other integer instrucions +;; Other integer instructions (define_insn_reservation "znver1_idirect" 1 (and (eq_attr "cpu" "znver1,znver2,znver3") (and (eq_attr "unit" "integer,unknown") @@ -807,7 +807,7 @@ "znver1-direct,znver1-load,znver1-fp1|znver1-fp2") ;; SSE moves -;; Fix me: Need to revist this again some of the moves may be restricted +;; Fix me: Need to revisit this again some of the moves may be restricted ;; to some fpu pipes. (define_insn_reservation "znver1_sse_mov" 2 (and (eq_attr "cpu" "znver1")
