https://gcc.gnu.org/g:d14633892c29ab94bafdf51f477009454e76defe

commit r17-1107-gd14633892c29ab94bafdf51f477009454e76defe
Author: Dhruv Chawla <[email protected]>
Date:   Wed May 20 11:34:31 2026 +0000

    ia64: Fix typos in various files
    
    Signed-off-by: Dhruv Chawla <[email protected]>
    
    gcc/ChangeLog:
    
            * config/ia64/ia64.cc (ia64_add_bundle_selector_before): Fix typos.
            * config/ia64/itanium2.md: Likewise.
            * config/ia64/sync.md: Likewise.

Diff:
---
 gcc/config/ia64/ia64.cc     | 2 +-
 gcc/config/ia64/itanium2.md | 4 ++--
 gcc/config/ia64/sync.md     | 4 ++--
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/gcc/config/ia64/ia64.cc b/gcc/config/ia64/ia64.cc
index 92ae6472c3cf..b06158ba7bc0 100644
--- a/gcc/config/ia64/ia64.cc
+++ b/gcc/config/ia64/ia64.cc
@@ -9150,7 +9150,7 @@ ia64_add_bundle_selector_before (int template0, rtx_insn 
*insn)
 /* The following function does insn bundling.  Bundling means
    inserting templates and nop insns to fit insn groups into permitted
    templates.  Instruction scheduling uses NDFA (non-deterministic
-   finite automata) encoding informations about the templates and the
+   finite automata) encoding information about the templates and the
    inserted nops.  Nondeterminism of the automata permits follows
    all possible insn sequences very fast.
 
diff --git a/gcc/config/ia64/itanium2.md b/gcc/config/ia64/itanium2.md
index 3ab68c3f840d..92b29b7cb623 100644
--- a/gcc/config/ia64/itanium2.md
+++ b/gcc/config/ia64/itanium2.md
@@ -554,7 +554,7 @@
 
 (define_reservation "2_B" "2_B0|2_B1")
 
-;; MLX bunlde uses ports equivalent to MFI bundles.
+;; MLX bundle uses ports equivalent to MFI bundles.
 
 ;;   For the MLI template, the I slot insn is always assigned to port I0
 ;; if it is in the first bundle or it is assigned to port I1 if it is in
@@ -899,7 +899,7 @@
        (not (match_test "bundling_p")))
   "2_I+2_only_ui0")
 
-;; There is only ony insn `mov ar.pfs =' for toar_i:
+;; There is only one insn `mov ar.pfs =' for toar_i:
 (define_insn_reservation "2_toar_i"  0
   (and (and (eq_attr "cpu" "itanium2")
             (eq_attr "itanium_class" "toar_i"))
diff --git a/gcc/config/ia64/sync.md b/gcc/config/ia64/sync.md
index 1b944b634dd0..4897e267e18f 100644
--- a/gcc/config/ia64/sync.md
+++ b/gcc/config/ia64/sync.md
@@ -101,7 +101,7 @@
    (match_operand:SI 7 "const_int_operand" "")]                        ;; fail 
model
   ""
 {
-  /* No need to distinquish __sync from __atomic, so get base value.  */
+  /* No need to distinguish __sync from __atomic, so get base value.  */
   enum memmodel model = memmodel_base (INTVAL (operands[6]));
   rtx ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
   rtx dval, eval;
@@ -201,7 +201,7 @@
    (match_operand:SI 3 "const_int_operand" "")]                        ;; succ 
model
   ""
 {
-  /* No need to distinquish __sync from __atomic, so get base value.  */
+  /* No need to distinguish __sync from __atomic, so get base value.  */
   enum memmodel model = memmodel_base (INTVAL (operands[3]));
 
   switch (model)

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