https://gcc.gnu.org/g:d97d828de87cab36da4795a7f5c2c05d4d951e3c
commit r17-1123-gd97d828de87cab36da4795a7f5c2c05d4d951e3c Author: Dhruv Chawla <[email protected]> Date: Wed May 20 12:11:37 2026 +0000 rs6000: Fix typos in various files Signed-off-by: Dhruv Chawla <[email protected]> gcc/ChangeLog: * config/rs6000/aix.h: Fix typos. * config/rs6000/cell.md: Likewise. * config/rs6000/darwin.h: Likewise. * config/rs6000/mmintrin.h: Likewise. * config/rs6000/rs6000-call.cc (rs6000_gimplify_va_arg): Likewise. * config/rs6000/rs6000-internal.h: Likewise. * config/rs6000/rs6000-logue.cc (is_altivec_return_reg): Likewise. (rs6000_output_function_prologue): Likewise. * config/rs6000/rs6000-p8swap.cc (quad_aligned_store_p): Likewise. (const_load_sequence_p): Likewise. (replace_swapped_aligned_store): Likewise. * config/rs6000/rs6000-passes.def: Likewise. * config/rs6000/rs6000-string.cc (expand_cmp_vec_sequence): Likewise. (expand_compare_loop): Likewise. * config/rs6000/rs6000.cc (rs6000_debug_addr_mask): Likewise. (rs6000_setup_reg_addr_masks): Likewise. (darwin_rs6000_override_options): Likewise. (rs6000_option_override_internal): Likewise. (rs6000_cost_data::determine_suggested_unroll_factor): Likewise. (rs6000_cannot_force_const_mem): Likewise. (rs6000_emit_le_vsx_move): Likewise. (rs6000_secondary_reload_memory): Likewise. (rs6000_reverse_condition): Likewise. (rs6000_expand_float128_convert): Likewise. (rs6000_adjust_atomic_subword): Likewise. (rs6000_expand_atomic_op): Likewise. (rs6000_xcoff_declare_object_name): Likewise. (output_pcrel_opt_reloc): Likewise. (rs6000_set_up_by_prologue): Likewise. (rs6000_split_logical_inner): Likewise. (rs6000_split_multireg_move): Likewise. * config/rs6000/rs6000.h: Likewise. * config/rs6000/rs6000.md: Likewise. * config/rs6000/sync.md: Likewise. * config/rs6000/vector.md: Likewise. * config/rs6000/vsx.md: Likewise. * config/rs6000/vxworks.h: Likewise. Diff: --- gcc/config/rs6000/aix.h | 2 +- gcc/config/rs6000/cell.md | 10 ++++---- gcc/config/rs6000/darwin.h | 2 +- gcc/config/rs6000/mmintrin.h | 2 +- gcc/config/rs6000/rs6000-call.cc | 2 +- gcc/config/rs6000/rs6000-internal.h | 2 +- gcc/config/rs6000/rs6000-logue.cc | 4 ++-- gcc/config/rs6000/rs6000-p8swap.cc | 6 ++--- gcc/config/rs6000/rs6000-passes.def | 2 +- gcc/config/rs6000/rs6000-string.cc | 10 ++++---- gcc/config/rs6000/rs6000.cc | 48 ++++++++++++++++++------------------- gcc/config/rs6000/rs6000.h | 4 ++-- gcc/config/rs6000/rs6000.md | 10 ++++---- gcc/config/rs6000/sync.md | 2 +- gcc/config/rs6000/vector.md | 4 ++-- gcc/config/rs6000/vsx.md | 8 +++---- gcc/config/rs6000/vxworks.h | 4 ++-- 17 files changed, 61 insertions(+), 61 deletions(-) diff --git a/gcc/config/rs6000/aix.h b/gcc/config/rs6000/aix.h index 89c8ad50be37..59d791912eb4 100644 --- a/gcc/config/rs6000/aix.h +++ b/gcc/config/rs6000/aix.h @@ -97,7 +97,7 @@ and __GLOBAL_AIXD_{libname} and are exported from each shared library. collect2 will detect these symbols when they exist in shared libraries that - the current program is being linked against. All such initiliser functions + the current program is being linked against. All such initialiser functions will be called prior to the constructors of the current program, and finaliser functions called after destructors. diff --git a/gcc/config/rs6000/cell.md b/gcc/config/rs6000/cell.md index da1c814a90c0..c5fb29f14f3e 100644 --- a/gcc/config/rs6000/cell.md +++ b/gcc/config/rs6000/cell.md @@ -44,7 +44,7 @@ ;; Dual issue exceptions: ;;(1) nop-pipelined FXU instr in slot 0 ;;(2) non-pipelined FPU inst in slot 0 -;; CSI instr(contex-synchronizing insn) +;; CSI instr(context-synchronizing insn) ;; Microcode insn ;; BRU unit: bru(none register stall), bru_cr(cr register stall) @@ -304,7 +304,7 @@ (eq_attr "cpu" "cell")) "fxu_cell+slot01") -; Basic FP latency is 10 cycles, thoughput is 1/cycle +; Basic FP latency is 10 cycles, throughput is 1/cycle (define_insn_reservation "cell-fp" 10 (and (eq_attr "type" "fp,fpsimple,dmul") (eq_attr "cpu" "cell")) @@ -315,13 +315,13 @@ (eq_attr "cpu" "cell")) "vsu1_cell+slot01") -;; sdiv thoughput 1/74, not pipelined but only in the FPU +;; sdiv throughput 1/74, not pipelined but only in the FPU (define_insn_reservation "cell-sdiv" 74 (and (eq_attr "type" "sdiv,ddiv") (eq_attr "cpu" "cell")) "slot1,nonpipeline,nonpipeline*72") -;; fsqrt thoughput 1/84, not pipelined but only in the FPU +;; fsqrt throughput 1/84, not pipelined but only in the FPU (define_insn_reservation "cell-sqrt" 84 (and (eq_attr "type" "ssqrt,dsqrt") (eq_attr "cpu" "cell")) @@ -410,7 +410,7 @@ ;; the target of VSU estimate should not be reused within 10 dispatch groups ;; the target of VSU float should not be reused within 8 dispatch groups ;; the target of VSU complex should not be reused within 5 dispatch groups -;; FP LOAD should not reuse an FPU Arithmetic target with 6 dispatch gropus +;; FP LOAD should not reuse an FPU Arithmetic target with 6 dispatch groups ;; mtctr-bcctr/bcctrl, branch target ctr register shadow update at ;; ex4 stage(10 cycles) diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h index 4717fb0d336f..175b6b1c3e08 100644 --- a/gcc/config/rs6000/darwin.h +++ b/gcc/config/rs6000/darwin.h @@ -99,7 +99,7 @@ since the functions are actually in libSystem but for 7.x compatibility we want them to be looked for in libmx first. Include libSystemStubs when compiling against 10.3 - 10.6 SDKs (we assume - this is the case when targetting these) - but not for 64-bit long double. + this is the case when targeting these) - but not for 64-bit long double. Don't do either for m64, the library is either a dummy or non-existent. */ diff --git a/gcc/config/rs6000/mmintrin.h b/gcc/config/rs6000/mmintrin.h index e2b587ebd049..12697eb9a95f 100644 --- a/gcc/config/rs6000/mmintrin.h +++ b/gcc/config/rs6000/mmintrin.h @@ -47,7 +47,7 @@ Most MMX intrinsic operations can be performed efficiently as C language 64-bit scalar operation or optimized to use the newer - 128-bit SSE/Altivec operations. We recomend this for new + 128-bit SSE/Altivec operations. We recommend this for new applications. */ #error "Please read comment above. Use -DNO_WARN_X86_INTRINSICS to disable this error." #endif diff --git a/gcc/config/rs6000/rs6000-call.cc b/gcc/config/rs6000/rs6000-call.cc index e31b147a3b92..85d270ccf00e 100644 --- a/gcc/config/rs6000/rs6000-call.cc +++ b/gcc/config/rs6000/rs6000-call.cc @@ -2572,7 +2572,7 @@ rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, std_gimplify_va_arg_expr that carries out the align adjust, for the case of relevance. We don't need to check for pass-by-reference because of the test above. - We can return a simplifed answer, since we know there's no offset to add. */ + We can return a simplified answer, since we know there's no offset to add. */ if (((TARGET_MACHO && rs6000_darwin64_abi) diff --git a/gcc/config/rs6000/rs6000-internal.h b/gcc/config/rs6000/rs6000-internal.h index 4af0955ec153..bb1e85cf9be5 100644 --- a/gcc/config/rs6000/rs6000-internal.h +++ b/gcc/config/rs6000/rs6000-internal.h @@ -1,5 +1,5 @@ /* Internal to rs6000 type, variable, and function declarations and - definitons shared between the various rs6000 source files. + definitions shared between the various rs6000 source files. Copyright (C) 1991-2026 Free Software Foundation, Inc. Contributed by Richard Kenner ([email protected]) diff --git a/gcc/config/rs6000/rs6000-logue.cc b/gcc/config/rs6000/rs6000-logue.cc index c6f162a46da1..960280caff07 100644 --- a/gcc/config/rs6000/rs6000-logue.cc +++ b/gcc/config/rs6000/rs6000-logue.cc @@ -282,7 +282,7 @@ is_altivec_return_reg (rtx reg, void *xyes) } -/* Return whether REG is a global user reg or has been specifed by +/* Return whether REG is a global user reg or has been specified by -ffixed-REG. We should not restore these, and so cannot use lmw or out-of-line restore functions if there are any. We also can't save them (well, emit frame notes for them), because frame @@ -4069,7 +4069,7 @@ rs6000_output_function_prologue (FILE *file) asm_fprintf (file, "\tmflr %s\n", reg_names[0]); /* In the ELFv2 ABI we have no compiler stack word. It must be - the resposibility of _mcount to preserve the static chain + the responsibility of _mcount to preserve the static chain register if required. */ if (DEFAULT_ABI != ABI_ELFv2 && cfun->static_chain_decl != NULL) diff --git a/gcc/config/rs6000/rs6000-p8swap.cc b/gcc/config/rs6000/rs6000-p8swap.cc index ca0c3c002811..f0c26c0265d5 100644 --- a/gcc/config/rs6000/rs6000-p8swap.cc +++ b/gcc/config/rs6000/rs6000-p8swap.cc @@ -456,7 +456,7 @@ quad_aligned_store_p (swap_web_entry *insn_entry, rtx_insn *insn) if (!rtx_equal_p (DF_REF_REG (use), swap_reg)) continue; - /* If there is no def or the def is artifical or there are + /* If there is no def or the def is artificial or there are multiple defs, punt. */ if (!def_link || !def_link->ref || DF_REF_IS_ARTIFICIAL (def_link->ref) || def_link->next) @@ -533,7 +533,7 @@ const_load_sequence_p (swap_web_entry *insn_entry, rtx insn) df_ref use; /* Iterate over the definitions that are used by this insn. Since - this is known to be a swap insn, expect only one used definnition. */ + this is known to be a swap insn, expect only one used definition. */ FOR_EACH_INSN_INFO_USE (use, insn_info) { struct df_link *def_link = DF_REF_CHAIN (use); @@ -1652,7 +1652,7 @@ replace_swapped_aligned_store (swap_web_entry *insn_entry, if (!rtx_equal_p (DF_REF_REG (use), swap_reg)) continue; - /* If there is no def or the def is artifical or there are + /* If there is no def or the def is artificial or there are multiple defs, we should not be here. */ gcc_assert (def_link && def_link->ref && !def_link->next && !DF_REF_IS_ARTIFICIAL (def_link->ref)); diff --git a/gcc/config/rs6000/rs6000-passes.def b/gcc/config/rs6000/rs6000-passes.def index 6276846b46bc..2b1d88f9e917 100644 --- a/gcc/config/rs6000/rs6000-passes.def +++ b/gcc/config/rs6000/rs6000-passes.def @@ -25,7 +25,7 @@ along with GCC; see the file COPYING3. If not see */ /* Pass to add the appropriate vector swaps on power8 little endian systems. - The power8 does not have instructions that automaticaly do the byte swaps + The power8 does not have instructions that automatically do the byte swaps for loads and stores. */ INSERT_PASS_BEFORE (pass_cse, 1, pass_analyze_swaps); diff --git a/gcc/config/rs6000/rs6000-string.cc b/gcc/config/rs6000/rs6000-string.cc index 35bb259c0242..062ff1e2465e 100644 --- a/gcc/config/rs6000/rs6000-string.cc +++ b/gcc/config/rs6000/rs6000-string.cc @@ -758,7 +758,7 @@ expand_cmp_vec_sequence (unsigned HOST_WIDE_INT bytes_to_compare, { /* Branch to cleanup code, otherwise fall through to do more compares. P8 and P9 use different CR bits because on P8 - we are looking at the result of a comparsion vs a + we are looking at the result of a comparison vs a register of zeroes so the all-true condition means no difference or zero was found. On P9, vcmpnezb sets a byte to 0xff if there is a mismatch or zero, so the all-false @@ -1405,7 +1405,7 @@ expand_compare_loop (rtx operands[]) /* Alignment is larger than word_mode so we do not need to be concerned with extra page crossings. But, we do not know that the length is larger than load_mode_size so we might - end up compareing against data before the block if we try + end up comparing against data before the block if we try an overlapping compare. Also we use this on P7 for fixed length remainder because P7 doesn't like overlapping unaligned. Strategy: load 8B, shift off bytes past length, and compare. */ @@ -1430,7 +1430,7 @@ expand_compare_loop (rtx operands[]) rtx nonconst_overlap = gen_label_rtx (); emit_label (nonconst_overlap); - /* Here we have to handle the case where whe have runtime + /* Here we have to handle the case where we have runtime length which may be too short for overlap compare, and alignment is not at least load_mode_size so we have to tread carefully to avoid stepping across 4k boundaries. */ @@ -1438,7 +1438,7 @@ expand_compare_loop (rtx operands[]) /* If the length after the loop was larger than word_mode size, we can just do an overlapping compare and we're done. We fall through to this code from the word_mode - compare that preceeds this. */ + compare that precedes this. */ do_overlap_load_compare (load_mode, false, 0, diff, cmp_rem, dcond, src1_addr, src2_addr, orig_src1, orig_src2); @@ -1632,7 +1632,7 @@ expand_compare_loop (rtx operands[]) produce the final result from memcmp. TARGET is the rtx for the register to receive the memcmp result. - SUB_RESULT is the rtx for the register contining the subtract result. */ + SUB_RESULT is the rtx for the register containing the subtract result. */ void generate_6432_conversion(rtx target, rtx sub_result) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index fba481b2b5de..5562d612b22f 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -191,7 +191,7 @@ int rs6000_vector_align[NUM_MACHINE_MODES]; reciprocal sqrt (frsqrte) for. */ unsigned char rs6000_recip_bits[MAX_MACHINE_MODE]; -/* Masks to determine which reciprocal esitmate instructions to generate +/* Masks to determine which reciprocal estimate instructions to generate automatically. */ enum rs6000_recip_mask { RECIP_SF_DIV = 0x001, /* Use divide estimate */ @@ -279,7 +279,7 @@ bool cpu_builtin_p = false; don't link in rs6000-c.cc, so we can't call it directly. */ void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT); -/* Simplfy register classes into simpler classifications. We assume +/* Simplify register classes into simpler classifications. We assume GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range check for standard register classes (gpr/floating/altivec/vsx) and floating/vector classes (float/altivec/vsx). */ @@ -338,7 +338,7 @@ static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = { /* Mask bits for each register class, indexed per mode. Historically the compiler has been more restrictive which types can do PRE_MODIFY instead of - PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */ + PRE_INC and PRE_DEC, so keep track of separate bits for these two. */ typedef unsigned char addr_mask_type; #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */ @@ -2173,7 +2173,7 @@ rs6000_debug_addr_mask (addr_mask_type mask, bool keep_spaces) return ret; } -/* Print the address masks in a human readble fashion. */ +/* Print the address masks in a human readable fashion. */ DEBUG_FUNCTION void rs6000_debug_print_mode (ssize_t m) { @@ -2711,7 +2711,7 @@ rs6000_setup_reg_addr_masks (void) || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR))))) addr_mask |= RELOAD_REG_OFFSET; - /* VSX registers can do REG+OFFSET addresssing if ISA 3.0 + /* VSX registers can do REG+OFFSET addressing if ISA 3.0 instructions are enabled. The offset for 128-bit VSX registers is only 12-bits. While GPRs can handle the full offset range, VSX registers can only handle the restricted range. */ @@ -3343,7 +3343,7 @@ darwin_rs6000_override_options (void) /* The linkers [ld64] that support 64Bit do not need the JBSR longcall optimisation, and will not work with the most generic case (where the - symbol is undefined external, but there is no symbl stub). */ + symbol is undefined external, but there is no symbol stub). */ if (TARGET_64BIT) rs6000_default_long_calls = 0; @@ -3997,7 +3997,7 @@ rs6000_option_override_internal (bool global_init_p) } /* Assume if the user asked for normal quad memory instructions, they want - the atomic versions as well, unless they explicity told us not to use quad + the atomic versions as well, unless they explicitly told us not to use quad word atomic instructions. */ if (TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC @@ -4152,7 +4152,7 @@ rs6000_option_override_internal (bool global_init_p) } /* Enable the default support for IEEE 128-bit floating point on Linux VSX - sytems. In GCC 7, we would enable the IEEE 128-bit floating point + systems. In GCC 7, we would enable the IEEE 128-bit floating point infrastructure (-mfloat128-type) but not enable the actual __float128 type unless the user used the explicit -mfloat128. In GCC 8, we enable both the keyword as well as the type. */ @@ -5528,7 +5528,7 @@ rs6000_cost_data::determine_suggested_unroll_factor (loop_vec_info loop_vinfo) { unsigned int epil_niter_unr = est_niter % unrolled_vf; unsigned int epil_niter = est_niter % vf; - /* Even if we have partial vector support, it can be still inefficent + /* Even if we have partial vector support, it can be still inefficient to calculate the length when the iteration count is unknown, so only expect it's good to unroll when the epilogue iteration count is not bigger than VF (only one time length calculation). */ @@ -9828,7 +9828,7 @@ rs6000_init_stack_protect_guard (void) static bool rs6000_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) { - /* If GET_CODE (x) is HIGH, the 'X' represets the high part of a symbol_ref. + /* If GET_CODE (x) is HIGH, the 'X' represents the high part of a symbol_ref. It can not be put into a constant pool. e.g. (high:DI (unspec:DI [(symbol_ref/u:DI ("*.LC0")..) (high:DI (symbol_ref:DI ("var")..)). */ @@ -10872,7 +10872,7 @@ rs6000_emit_le_vsx_move (rtx dest, rtx source, machine_mode mode) } /* Return whether a SFmode or SImode move can be done without converting one - mode to another. This arrises when we have: + mode to another. This arises when we have: (SUBREG:SF (REG:SI ...)) (SUBREG:SI (REG:SF ...)) @@ -12627,7 +12627,7 @@ rs6000_secondary_reload_memory (rtx addr, } /* Helper function for rs6000_secondary_reload to return true if a move to a - different register classe is really a simple move. */ + different register class is really a simple move. */ static bool rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type, @@ -15293,7 +15293,7 @@ rs6000_reverse_condition (machine_mode mode, enum rtx_code code) return reverse_condition (code); } -/* Check if C (as 64bit integer) can be rotated to a constant which constains +/* Check if C (as 64bit integer) can be rotated to a constant which contains nonzero bits at the LOWBITS low bits only. Return true if C can be rotated to such constant. If so, *ROT is written @@ -15629,7 +15629,7 @@ rs6000_expand_float128_convert (rtx dest, rtx src, bool unsigned_p) rtx_2func_t to_di_sign; rtx_2func_t to_di_uns; } hw_conversions[2] = { - /* convertions to/from KFmode */ + /* conversions to/from KFmode */ { gen_extenddfkf2_hw, /* KFmode <- DFmode. */ gen_extendsfkf2_hw, /* KFmode <- SFmode. */ @@ -15645,7 +15645,7 @@ rs6000_expand_float128_convert (rtx dest, rtx src, bool unsigned_p) gen_fixuns_kfdi2_hw, /* DImode <- KFmode (unsigned). */ }, - /* convertions to/from TFmode */ + /* conversions to/from TFmode */ { gen_extenddftf2_hw, /* TFmode <- DFmode. */ gen_extendsftf2_hw, /* TFmode <- SFmode. */ @@ -16919,7 +16919,7 @@ rs6000_adjust_atomic_subword (rtx orig_mem, rtx *pshift, rtx *pmask) } /* A subroutine of the various atomic expanders. For sub-word operands, - combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */ + combine OLDVAL and NEWVAL via MASK. Returns a new pseudo. */ static rtx rs6000_mask_atomic_subword (rtx oldval, rtx newval, rtx mask) @@ -17251,7 +17251,7 @@ rs6000_expand_atomic_op (enum rtx_code code, rtx mem, rtx val, if (shift) { /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and - then do the calcuations in a SImode register. */ + then do the calculations in a SImode register. */ if (orig_before) rs6000_finish_atomic_subword (orig_before, before, shift); if (orig_after) @@ -17260,7 +17260,7 @@ rs6000_expand_atomic_op (enum rtx_code code, rtx mem, rtx val, else if (store_mode != mode) { /* QImode/HImode on machines with lbarx/lharx where we do the native - operation and then do the calcuations in a SImode register. */ + operation and then do the calculations in a SImode register. */ if (orig_before) convert_move (orig_before, before, 1); if (orig_after) @@ -22085,7 +22085,7 @@ rs6000_xcoff_declare_object_name (FILE *file, const char *name, tree decl) &data, true); } -/* Overide the default 'SYMBOL-.' syntax with AIX compatible 'SYMBOL-$'. */ +/* Override the default 'SYMBOL-.' syntax with AIX compatible 'SYMBOL-$'. */ void rs6000_asm_output_dwarf_pcrel (FILE *file, int size, const char *label) @@ -27000,10 +27000,10 @@ output_pcrel_opt_reloc (rtx label_num) In the PowerPC, we use this to adjust the length of an instruction if one or more prefixed instructions are generated, using the attribute num_prefixed_insns. A prefixed instruction is 8 bytes instead of 4, but the - hardware requires that a prefied instruciton does not cross a 64-byte + hardware requires that a prefied instruction does not cross a 64-byte boundary. This means the compiler has to assume the length of the first prefixed instruction is 12 bytes instead of 8 bytes. Since the length is - already set for the non-prefixed instruction, we just need to udpate for the + already set for the non-prefixed instruction, we just need to update for the difference. */ int @@ -27123,7 +27123,7 @@ rs6000_set_up_by_prologue (struct hard_reg_set_container *set) /* Helper function for rs6000_split_logical to emit a logical instruction after - spliting the operation to single GPR registers. + splitting the operation to single GPR registers. DEST is the destination register. OP1 and OP2 are the input source registers. @@ -27171,7 +27171,7 @@ rs6000_split_logical_inner (rtx dest, } /* Optimize IOR/XOR of 0 to be a simple move. Split large operations - into separate ORI/ORIS or XORI/XORIS instrucitons. */ + into separate ORI/ORIS or XORI/XORIS instructions. */ else if (code == IOR || code == XOR) { if (value == 0) @@ -27430,7 +27430,7 @@ rs6000_split_multireg_move (rtx dst, rtx src) /* TDmode residing in FP registers is special, since the ISA requires that the lower-numbered word of a register pair is always the most significant word, even in little-endian mode. This does not match the usual subreg - semantics, so we cannnot use simplify_gen_subreg in those cases. Access + semantics, so we cannot use simplify_gen_subreg in those cases. Access the appropriate constituent registers "by hand" in little-endian mode. Note we do not need to check for destructive overlap here since TDmode diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index af233a049a96..91897d37fe62 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1778,10 +1778,10 @@ extern scalar_int_mode rs6000_pmode; In the PowerPC, we use this to adjust the length of an instruction if one or more prefixed instructions are generated, using the attribute num_prefixed_insns. A prefixed instruction is 8 bytes instead of 4, but the - hardware requires that a prefied instruciton does not cross a 64-byte + hardware requires that a prefied instruction does not cross a 64-byte boundary. This means the compiler has to assume the length of the first prefixed instruction is 12 bytes instead of 8 bytes. Since the length is - already set for the non-prefixed instruction, we just need to udpate for the + already set for the non-prefixed instruction, we just need to update for the difference. */ #define ADJUST_INSN_LENGTH(INSN,LENGTH) \ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 3089551552c8..2ccbe178bb53 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -334,7 +334,7 @@ (const_string "no"))) -;; Whether an insn loads an external address for the PCREL_OPT optimizaton. +;; Whether an insn loads an external address for the PCREL_OPT optimization. (define_attr "loads_external_address" "no,yes" (const_string "no")) @@ -6696,7 +6696,7 @@ xsrdpiz %x0,%x1" [(set_attr "type" "fp")]) -;; Opitmize converting SF/DFmode to signed SImode and back to SF/DFmode. This +;; Optimize converting SF/DFmode to signed SImode and back to SF/DFmode. This ;; optimization prevents on ISA 2.06 systems and earlier having to store the ;; value from the FPR/vector unit to the stack, load the value into a GPR, sign ;; extend it, store it back on the stack from the GPR, load it back into the @@ -9544,7 +9544,7 @@ ;; individual 32-bit parts across. Subreg doesn't work too well on the TF ;; value, since it is allocated in reload and not all of the flow information ;; is setup for it. We have two patterns to do the two moves between gprs and -;; fprs. There isn't a dependancy between the two, but we could potentially +;; fprs. There isn't a dependency between the two, but we could potentially ;; schedule other instructions between the two instructions. (define_insn "p8_fmrgow_<mode>" @@ -11714,7 +11714,7 @@ (const_int 8)))]) ;; Call to indirect functions with the AIX abi using a 3 word descriptor. -;; Operand0 is the addresss of the function to call +;; Operand0 is the address of the function to call ;; Operand3 is the location in the function descriptor to load r2 from ;; Operand4 is the offset of the stack location holding the current TOC pointer @@ -11758,7 +11758,7 @@ (const_string "12")))]) ;; Call to indirect functions with the ELFv2 ABI. -;; Operand0 is the addresss of the function to call +;; Operand0 is the address of the function to call ;; Operand3 is the offset of the stack location holding the current TOC pointer (define_insn "*call_indirect_elfv2<mode>" diff --git a/gcc/config/rs6000/sync.md b/gcc/config/rs6000/sync.md index a4e8344ef114..008aaf849378 100644 --- a/gcc/config/rs6000/sync.md +++ b/gcc/config/rs6000/sync.md @@ -265,7 +265,7 @@ DONE; }) -;; Any supported integer mode that has atomic l<x>arx/st<x>cx. instrucitons +;; Any supported integer mode that has atomic l<x>arx/st<x>cx. instructions ;; other than the quad memory operations, which have special restrictions. ;; Byte/halfword atomic instructions were added in ISA 2.06B, but were phased ;; in and did not show up until power8. TImode atomic lqarx/stqcx. require diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index e6adf91002ed..22eee2f81f05 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -46,7 +46,7 @@ ;; Vector arithmetic modes (define_mode_iterator VEC_A [V16QI V8HI V4SI V2DI V4SF V2DF]) -;; Vector modes that need alginment via permutes +;; Vector modes that need alignment via permutes (define_mode_iterator VEC_K [V16QI V8HI V4SI V4SF]) ;; Vector logical modes @@ -1300,7 +1300,7 @@ DONE; }) -;; Vector shift right in bits. Currently supported ony for shift +;; Vector shift right in bits. Currently supported only for shift ;; amounts that can be expressed as byte shifts (divisible by 8). ;; General shift amounts can be supported using vsro + vsr. We're ;; not expecting to see these yet (the vectorizer currently diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index f5ace28ea93a..1305eff8cddb 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -5595,7 +5595,7 @@ emit_insn (gen_vcmpne<VSX_EXTRACT_WIDTH> (cmpz2_result, operands[2], vzero)); emit_insn (gen_and<mode>3 (and_result, cmpz1_result, cmpz2_result)); - /* Vector with ones in elments that do not match. */ + /* Vector with ones in elements that do not match. */ emit_insn (gen_vcmpnez<VSX_EXTRACT_WIDTH> (cmpz_result, operands[1], operands[2])); @@ -5683,7 +5683,7 @@ emit_insn (gen_vcmpne<VSX_EXTRACT_WIDTH> (cmpz2_result, operands[2], vzero)); emit_insn (gen_and<mode>3 (and_result, cmpz1_result, cmpz2_result)); - /* Vector with ones in elments that match. */ + /* Vector with ones in elements that match. */ emit_insn (gen_vcmpnez<VSX_EXTRACT_WIDTH> (cmpz_result, operands[1], operands[2])); emit_insn (gen_one_cmpl<mode>2 (not_cmpz_result, cmpz_result)); @@ -6714,8 +6714,8 @@ else { /* Reverse value of byte element indexes by XORing with 0xFF. - Reverse the 32-byte section identifier match by subracting bits [0:2] - of elemet from 7. */ + Reverse the 32-byte section identifier match by subtracting bits [0:2] + of element from 7. */ int value = INTVAL (operands[4]); rtx vreg = gen_reg_rtx (V16QImode); diff --git a/gcc/config/rs6000/vxworks.h b/gcc/config/rs6000/vxworks.h index 1ea5fd715295..e5e6e3e9b858 100644 --- a/gcc/config/rs6000/vxworks.h +++ b/gcc/config/rs6000/vxworks.h @@ -187,7 +187,7 @@ along with GCC; see the file COPYING3. If not see /* Leverage linker relaxation for RTPs. This helps 32bit programs referring to kernel services too far away for short calls, is more - precise than -mlongcall and can be overriden with -Wl,--no-relax. */ + precise than -mlongcall and can be overridden with -Wl,--no-relax. */ #define VXWORKS_RELAX_LINK_SPEC "%{mrtp:--relax}" /*-------------------------------------------------------------*/ @@ -298,7 +298,7 @@ along with GCC; see the file COPYING3. If not see This is essentially the linux64.h version with an extra guard on TARGET_VXWORKS_RTP to avoid DW_EH_PE_indirect in 64bit DKMs as they could result in references from one DKM to resolve to symbols exposed - by a previsouly loaded DKM even if the symbol is also provided by the + by a previously loaded DKM even if the symbol is also provided by the DKM where the reference takes place. */ #undef ASM_PREFERRED_EH_DATA_FORMAT #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
