https://gcc.gnu.org/g:567dd0359ef41e1750e1e656995a8e4f41018e07
commit r17-1109-g567dd0359ef41e1750e1e656995a8e4f41018e07 Author: Dhruv Chawla <[email protected]> Date: Wed May 20 11:37:44 2026 +0000 loongarch: Fix typos in various files Signed-off-by: Dhruv Chawla <[email protected]> gcc/ChangeLog: * config/loongarch/lasx.md: Fix typos. * config/loongarch/loongarch-builtins.cc: Likewise. * config/loongarch/loongarch-c.cc (loongarch_pragma_target_parse): Likewise. * config/loongarch/loongarch-opts.cc (loongarch_generate_mrecip_scheme): Likewise. * config/loongarch/loongarch-opts.h (loongarch_config_target): Likewise. * config/loongarch/loongarch.cc (loongarch_setup_incoming_varargs): Likewise. (loongarch_build_integer): Likewise. (loongarch_explicit_relocs_p): Likewise. (loongarch_valid_lo_sum_p): Likewise. (loongarch_addu16i_imm12_operand_p): Likewise. (loongarch_rewrite_mem_for_simple_ldst): Likewise. (loongarch_is_elem_duplicate): Likewise. (loongarch_expand_vec_perm_const): Likewise. (loongarch_sched_reassociation_width): Likewise. (loongarch_expand_vec_unpack): Likewise. (dispatch_function_versions): Likewise. (loongarch_option_same_function_versions): Likewise. * config/loongarch/loongarch.h: Likewise. * config/loongarch/loongarch.md: Likewise. * config/loongarch/lsx.md: Likewise. * config/loongarch/predicates.md: Likewise. * config/loongarch/simd.md: Likewise. * config/loongarch/sync.md: Likewise. Diff: --- gcc/config/loongarch/lasx.md | 2 +- gcc/config/loongarch/loongarch-builtins.cc | 2 +- gcc/config/loongarch/loongarch-c.cc | 2 +- gcc/config/loongarch/loongarch-opts.cc | 2 +- gcc/config/loongarch/loongarch-opts.h | 2 +- gcc/config/loongarch/loongarch.cc | 36 +++++++++++++++--------------- gcc/config/loongarch/loongarch.h | 2 +- gcc/config/loongarch/loongarch.md | 4 ++-- gcc/config/loongarch/lsx.md | 2 +- gcc/config/loongarch/predicates.md | 6 ++--- gcc/config/loongarch/simd.md | 4 ++-- gcc/config/loongarch/sync.md | 2 +- 12 files changed, 33 insertions(+), 33 deletions(-) diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md index d606bf061d02..71bbaaa475c9 100644 --- a/gcc/config/loongarch/lasx.md +++ b/gcc/config/loongarch/lasx.md @@ -193,7 +193,7 @@ (V8SI "V8HI") (V4DI "V4SI")]) -;; Double-sized Vector MODE with same elemet type. "Vector, Enlarged-MODE" +;; Double-sized Vector MODE with same element type. "Vector, Enlarged-MODE" (define_mode_attr VEMODE256 [(V8SF "V16SF") (V8SI "V16SI") diff --git a/gcc/config/loongarch/loongarch-builtins.cc b/gcc/config/loongarch/loongarch-builtins.cc index f7aae038671c..14bd9d247412 100644 --- a/gcc/config/loongarch/loongarch-builtins.cc +++ b/gcc/config/loongarch/loongarch-builtins.cc @@ -904,7 +904,7 @@ static const struct loongarch_builtin_description loongarch_builtins[] = { DIRECT_NO_TARGET_BUILTIN (ldpte_d, LARCH_VOID_FTYPE_DI_UQI, la64), DIRECT_NO_TARGET_BUILTIN (ldpte_w, LARCH_VOID_FTYPE_SI_UQI, la64_or_la32s), - /* CRC Instrinsic */ + /* CRC Intrinsic */ DIRECT_BUILTIN (crc_w_b_w, LARCH_SI_FTYPE_QI_SI, la64), DIRECT_BUILTIN (crc_w_h_w, LARCH_SI_FTYPE_HI_SI, la64), diff --git a/gcc/config/loongarch/loongarch-c.cc b/gcc/config/loongarch/loongarch-c.cc index 9556641bd1d7..84d32acf1c90 100644 --- a/gcc/config/loongarch/loongarch-c.cc +++ b/gcc/config/loongarch/loongarch-c.cc @@ -235,7 +235,7 @@ loongarch_pragma_target_parse (tree args, tree pop_target) cpp_opts->warn_unused_macros = saved_warn_unused_macros; - /* If we're popping or reseting make sure to update the globals so that + /* If we're popping or resetting make sure to update the globals so that the optab availability predicates get recomputed. */ if (pop_target) loongarch_save_restore_target_globals (pop_target); diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc index 0fa393b90285..e0fa33796703 100644 --- a/gcc/config/loongarch/loongarch-opts.cc +++ b/gcc/config/loongarch/loongarch-opts.cc @@ -985,7 +985,7 @@ loongarch_generate_mrecip_scheme (unsigned int mask) -/* Refresh the switches acccording to the resolved loongarch_target struct. */ +/* Refresh the switches according to the resolved loongarch_target struct. */ void loongarch_target_option_override (struct loongarch_target *target, struct gcc_options *opts, diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h index 69691aa3be53..96867750336c 100644 --- a/gcc/config/loongarch/loongarch-opts.h +++ b/gcc/config/loongarch/loongarch-opts.h @@ -52,7 +52,7 @@ loongarch_config_target (struct loongarch_target *target, int follow_multilib_list_p); -/* Refresh the switches acccording to the resolved loongarch_target struct. */ +/* Refresh the switches according to the resolved loongarch_target struct. */ void loongarch_target_option_override (struct loongarch_target *target, struct gcc_options *opts, diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index 0831da018ff2..401119715012 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -177,7 +177,7 @@ int loongarch_dwarf_regno[FIRST_PSEUDO_REGISTER]; static bool loongarch_hard_regno_mode_ok_p[MAX_MACHINE_MODE] [FIRST_PSEUDO_REGISTER]; -/* Index C is true if character C is a valid PRINT_OPERAND punctation +/* Index C is true if character C is a valid PRINT_OPERAND punctuation character. */ static bool loongarch_print_operand_punct[256]; @@ -767,8 +767,8 @@ loongarch_setup_incoming_varargs (cumulative_args_t cum, local_cum = *get_cumulative_args (cum); /* For a C23 variadic function w/o any named argument, and w/o an - artifical argument for large return value, skip advancing args. - There is such an artifical argument iff. arg.type is non-NULL + artificial argument for large return value, skip advancing args. + There is such an artificial argument iff. arg.type is non-NULL (PR 114175). */ if (!TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (current_function_decl)) || arg.type != NULL_TREE) @@ -1620,7 +1620,7 @@ loongarch_build_integer (struct loongarch_integer_op *codes, /* Determine whether the upper 32 bits are sign-extended from the lower 32 bits. If it is, the instructions to load the high order can be - ommitted. */ + omitted. */ if (lu32i[sign31] && lu52i[sign31]) return cost; /* If the lower 32 bits are the same as the upper 32 bits, just copy @@ -1665,7 +1665,7 @@ loongarch_build_integer (struct loongarch_integer_op *codes, /* Fill CODES with a sequence of rtl operations to load VALUE. Return the number of operations needed. - Split interger in loongarch_output_move. */ + Split integer in loongarch_output_move. */ static unsigned int loongarch_integer_cost (HOST_WIDE_INT value) @@ -2272,7 +2272,7 @@ loongarch_explicit_relocs_p (enum loongarch_symbol_type type) /* If we are performing LTO for a final link, and we have the linker plugin so we know the resolution of the symbols, then all GOT references are binding to external symbols or - preemptable symbols. So the linker cannot relax them. */ + preemptible symbols. So the linker cannot relax them. */ return (in_lto_p && !flag_incremental_link && HAVE_LTO_PLUGIN == 2 @@ -2466,7 +2466,7 @@ loongarch_valid_lo_sum_p (enum loongarch_symbol_type symbol_type, if (!loongarch_split_symbol_type (symbol_type)) return false; - /* We can't tell size or alignment when we have BLKmode, so try extracing a + /* We can't tell size or alignment when we have BLKmode, so try extracting a decl from the symbol if possible. */ if (mode == BLKmode) { @@ -4932,7 +4932,7 @@ loongarch_addu16i_imm12_operand_p (HOST_WIDE_INT value, machine_mode mode) } /* Split one integer constant op[0] into two (op[1] and op[2]) for constant - plus operation in a specific mode. The splitted constants can be added + plus operation in a specific mode. The split constants can be added onto a register with a single instruction (addi.{d/w} or addu16i.d). */ void @@ -6445,7 +6445,7 @@ loongarch_rewrite_mem_for_simple_ldst (rtx mem) return new_mem; } -/* Print the text for PRINT_OPERAND punctation character CH to FILE. +/* Print the text for PRINT_OPERAND punctuation character CH to FILE. The punctuation characters are: '.' Print the name of the register with a hard-wired zero (zero or $r0). @@ -9615,9 +9615,9 @@ loongarch_is_elem_duplicate (struct expand_vec_perm_d *d) /* In LASX, some permutation insn does not have the behavior that gcc expects when compiler wants to emit a vector permutation. - 1. What GCC provides via vectorize_vec_perm_const ()'s paramater: + 1. What GCC provides via vectorize_vec_perm_const ()'s parameter: When GCC wants to performs a vector permutation, it provides two op - reigster, one target register, and a selector. + register, one target register, and a selector. In const vector permutation case, GCC provides selector as a char array that contains original value; in variable vector permutation (performs via vec_perm<mode> insn template), it provides a vector register. @@ -9803,8 +9803,8 @@ loongarch_expand_vec_perm_const (struct expand_vec_perm_d *d) idx = d->perm[0]; /* We will use xvrepl128vei.* insn to achieve the result, but we need to make the high/low 128bit has the same contents that contain the - value that we need to broardcast, because xvrepl128vei does the - broardcast job from every 128bit of source register to + value that we need to broadcast, because xvrepl128vei does the + broadcast job from every 128bit of source register to corresponded part of target register! (A deep sigh.) */ if (idx < d->nelt / 2) { @@ -10045,7 +10045,7 @@ loongarch_sched_reassociation_width (unsigned int opc, machine_mode mode) return loongarch_cpu_sched_reassociation_width (&la_target, opc, mode); } -/* Implement extract a scalar element from vecotr register */ +/* Implement extract a scalar element from vector register */ void loongarch_expand_vector_extract (rtx target, rtx vec, int elt) @@ -10279,7 +10279,7 @@ loongarch_expand_vec_unpack (rtx operands[2], bool unsigned_p) if (!unsigned_p) { - /* Extract sign extention for each element comparing each element + /* Extract sign extension for each element comparing each element with immediate zero. */ tmp = gen_reg_rtx (imode); emit_insn (cmpFunc (tmp, operands[1], CONST0_RTX (imode))); @@ -11895,7 +11895,7 @@ dispatch_function_versions (tree dispatch_decl, gseq = bb_seq (*empty_bb); /* Function version dispatch is via IFUNC. IFUNC resolvers fire before - constructors, so explicity call __init_loongarch_feature_bits here. */ + constructors, so explicitly call __init_loongarch_feature_bits here. */ tree init_fn_type = build_function_type_list (void_type_node, void_type_node, NULL); @@ -12151,10 +12151,10 @@ loongarch_option_same_function_versions (string_slice str1, const_tree, /* Output assembly to materialize the address of the stack canary value into reg. The third argument, tmp, should be and should only be non-NULL if the extreme code model is effective for the canary. If - the fourth arugment, load, is true, the canary value is loaded into + the fourth argument, load, is true, the canary value is loaded into the register. - The assembly cannot be splitted due to security reason. */ + The assembly cannot be split due to security reason. */ void loongarch_output_asm_load_canary (rtx reg, rtx canary, rtx tmp) { diff --git a/gcc/config/loongarch/loongarch.h b/gcc/config/loongarch/loongarch.h index 4d9acd8ca7c5..3339040a4335 100644 --- a/gcc/config/loongarch/loongarch.h +++ b/gcc/config/loongarch/loongarch.h @@ -1073,7 +1073,7 @@ typedef struct { ... .uleb128 foo-$LFBxxx - The .uleb128 requies $LFBxxx to match the FDE start address, which is + The .uleb128 requires $LFBxxx to match the FDE start address, which is likewise a byte pointer rather than an ISA-encoded address. At the time of writing, this hook is not used for the function end diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index fe6d28e76161..5c4f8dfb5b57 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -360,7 +360,7 @@ ;; Length of instruction in bytes. (define_attr "length" "" (cond [ - ;; Branch futher than +/- 128 KiB require two instructions. + ;; Branch further than +/- 128 KiB require two instructions. (eq_attr "type" "branch") (if_then_else (and (le (minus (match_dup 0) (pc)) (const_int 131064)) (le (minus (pc) (match_dup 0)) (const_int 131068))) @@ -2074,7 +2074,7 @@ [(set_attr "type" "fcvt") (set_attr "mode" "<ANYF:MODE>")]) -;; conversion of an integeral (or boolean) value to a floating-point value +;; conversion of an integral (or boolean) value to a floating-point value (define_insn "floatsidf2" [(set (match_operand:DF 0 "register_operand" "=f") diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md index 2418e62722a7..66359949a42b 100644 --- a/gcc/config/loongarch/lsx.md +++ b/gcc/config/loongarch/lsx.md @@ -167,7 +167,7 @@ (V4SI "V4HI") (V2DI "V2SI")]) -;; Double-sized Vector MODE with same elemet type. "Vector, Enlarged-MODE" +;; Double-sized Vector MODE with same element type. "Vector, Enlarged-MODE" (define_mode_attr VEMODE [(V4SF "V8SF") (V4SI "V8SI") diff --git a/gcc/config/loongarch/predicates.md b/gcc/config/loongarch/predicates.md index af3b770c4e9d..9e6868465147 100644 --- a/gcc/config/loongarch/predicates.md +++ b/gcc/config/loongarch/predicates.md @@ -430,8 +430,8 @@ (match_code "const,symbol_ref,label_ref") { /* Split symbol to high and low if return false. - If defined TARGET_CMODEL_EXTREME, all symbol would be splited, - else if offset is not zero, the symbol would be splited. */ + If defined TARGET_CMODEL_EXTREME, all symbol would be split, + else if offset is not zero, the symbol would be split. */ enum loongarch_symbol_type symbol_type; loongarch_symbolic_constant_p (op, &symbol_type); @@ -447,7 +447,7 @@ return true; /* When compiling with '-mcmodel=medium -mexplicit-relocs' - symbols are splited in loongarch_legitimize_call_address. + symbols are split in loongarch_legitimize_call_address. When compiling with '-mcmodel=medium -mno-explicit-relocs', first obtain the symbolic address or the address of the diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md index 3d1e3e7a787a..377e94fb356a 100644 --- a/gcc/config/loongarch/simd.md +++ b/gcc/config/loongarch/simd.md @@ -373,7 +373,7 @@ !flag_trapping_math") ;; fix_trunc is allowed to raise inexact exception even if -;; -fno-fp-int-builtin-inexact. Because the middle end trys to match +;; -fno-fp-int-builtin-inexact. Because the middle end tries to match ;; (FIX x) and it does not know (FIX (UNSPEC_SIMD_FRINTRZ x)), we need ;; to use define_insn_and_split instead of define_expand (expanders are ;; not considered during matching). @@ -548,7 +548,7 @@ [(set_attr "type" "simd_fcmp") (set_attr "mode" "<MODE>")]) -;; <x>vfcmp.*.{s/d} instructions only as instrinsics +;; <x>vfcmp.*.{s/d} instructions only as intrinsics (define_c_enum "unspec" [UNSPEC_SIMD_FCMP_CAF UNSPEC_SIMD_FCMP_SAF diff --git a/gcc/config/loongarch/sync.md b/gcc/config/loongarch/sync.md index de7b9eb890b3..c7692412331b 100644 --- a/gcc/config/loongarch/sync.md +++ b/gcc/config/loongarch/sync.md @@ -74,7 +74,7 @@ ;; [1]: https://git.kernel.org/torvalds/c/e031a5f3f1ed ;; ;; Implementations without support for the finer-granularity hints simply treat -;; all as the full barrier (DBAR 0), so we can unconditionally start emiting the +;; all as the full barrier (DBAR 0), so we can unconditionally start emitting the ;; more precise hints right away. (define_insn "mem_thread_fence_1" [(set (match_operand:BLK 0 "" "")
