https://gcc.gnu.org/g:17aa19392a652194ec12badc2fcac9535329fbac
commit r16-9201-g17aa19392a652194ec12badc2fcac9535329fbac Author: Xin Liu <[email protected]> Date: Tue Jun 23 02:01:13 2026 +0000 i386: Add HYGON c86-4g-m8 support Add c86-4g-m8 as a new HYGON Family 18h model 8 processor. It inherits the c86-4g-m7 ISA set and most tuning decisions, including the same processor costs and scheduling model baseline. The patch wires c86-4g-m8 into the common x86 processor tables, driver CPU detection, target macros, --with-arch/--with-cpu handling, builtin CPU detection and documentation. It also extends the c86-4g tuning masks that already special-case c86-4g-m7 to cover c86-4g-m8. For scheduling, rename the shared scheduling description file from gcc/config/i386/c86-4g-m7.md to gcc/config/i386/c86-4g-m7m8.md and reuse the c86-4g-m7 scheduling reservations for c86-4g-m8 where the latency and resource usage are the same. Add separate c86-4g-m8 reservations for the few operations with different latency. This patch does not affect genautomata build time. gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_hygon_cpu): Detect HYGON Family 18h model 8 as c86-4g-m8. * common/config/i386/i386-common.cc (processor_names): Add c86-4g-m8. (processor_alias_table): Likewise. * common/config/i386/i386-cpuinfo.h (enum processor_subtypes): Add HYGONFAM18H_C86_4G_M8. * config.gcc: Add c86-4g-m8 to supported x86 CPUs and handle c86_4g_m8 target triples. * config/i386/c86-4g-m7.md: Rename to ... * config/i386/c86-4g-m7m8.md: ... this and extend shared c86-4g-m7 scheduling reservations to c86-4g-m8. (c86_4g_m8_imovx_cwde): New reservation. (c86_4g_m7_imov_xchg): Add c86_4g_m8 to CPU attribute. (c86_4g_m7_imov_xchg_load): Ditto. (c86_4g_m7_imov): Ditto. (c86_4g_m7_imov_load): Ditto. (c86_4g_m7_imov_store): Ditto. (c86_4g_m7_push): Ditto. (c86_4g_m7_push_mem): Ditto. (c86_4g_m7_pop): Ditto. (c86_4g_m7_pop_mem): Ditto. (c86_4g_m7_imul): Ditto. (c86_4g_m7_imul_load): Ditto. (c86_4g_m7_idiv): Ditto. (c86_4g_m7_idiv_QI): Ditto. (c86_4g_m7_idiv_load): Ditto. (c86_4g_m7_idiv_QI_load): Ditto. (c86_4g_m7_insn): Ditto. (c86_4g_m7_insn_load): Ditto. (c86_4g_m7_insn_store): Ditto. (c86_4g_m7_insn2_store): Ditto. (c86_4g_m7_insn_both): Ditto. (c86_4g_m7_setcc): Ditto. (c86_4g_m7_setcc_load): Ditto. (c86_4g_m7_setcc_store): Ditto. (c86_4g_m7_alu1_double): Ditto. (c86_4g_m7_alu1_double_load): Ditto. (c86_4g_m7_alu1_vector): Ditto. (c86_4g_m7_alu1_vector_load): Ditto. (c86_4g_m7_alu1_direct): Ditto. (c86_4g_m7_alu1_direct_load): Ditto. (c86_4g_m7_call): Ditto. (c86_4g_m7_branch): Ditto. (c86_4g_m7_branch_load): Ditto. (c86_4g_m7_lea): Ditto. (c86_4g_m7_leave): Ditto. (c86_4g_m7_str): Ditto. (c86_4g_m7_str_load): Ditto. (c86_4g_m7_ieu_vector): Ditto. (c86_4g_m7_ieu_vector_load): Ditto. (c86_4g_m7_sse_insertimm): Ditto. (c86_4g_m7_sse_insert): Ditto. (c86_4g_m7_fp_cmov): Ditto. (c86_4g_m7_fp_mov_direct_load): Ditto. (c86_4g_m7_fp_mov_direct_store): Ditto. (c86_4g_m7_fp_mov_double_load): Ditto. (c86_4g_m7_fp_mov_double_store): Ditto. (c86_4g_m7_fp_mov_direct): Ditto. (c86_4g_m7_fp_sqrt): Ditto. (c86_4g_m7_fp_spc_direct): Ditto. (c86_4g_m7_fp_spc): Ditto. (c86_4g_m7_fp_op_mul): Ditto. (c86_4g_m7_fp_op_mul_load): Ditto. (c86_4g_m7_fp_op_imul_load): Ditto. (c86_4g_m7_fp_div): Ditto. (c86_4g_m7_fp_div_load): Ditto. (c86_4g_m7_fp_idiv_load): Ditto. (c86_4g_m7_fp_fsgn): Ditto. (c86_4g_m7_fp_fcmp): Ditto. (c86_4g_m7_fp_fcmp_load): Ditto. (c86_4g_m7_fp_mmx): Ditto. (c86_4g_m7_mmx_add_cmp): Ditto. (c86_4g_m7_mmx_add_cmp_load): Ditto. (c86_4g_m7_mmx_cvt): Ditto. (c86_4g_m7_mmx_cvt_load): Ditto. (c86_4g_m7_mmx_shift): Ditto. (c86_4g_m7_mmx_shift_load): Ditto. (c86_4g_m7_mmx_shift_avg): Ditto. (c86_4g_m7_mmx_shift_avg_load): Ditto. (c86_4g_m7_mmx_shift_sadbw): Ditto. (c86_4g_m7_mmx_shift_sadbw_load): Ditto. (c86_4g_m7_mmx_mov): Ditto. (c86_4g_m7_mmx_mov_store): Ditto. (c86_4g_m7_mmx_mov_load): Ditto. (c86_4g_m7_mmx_mul): Ditto. (c86_4g_m7_mmx_mul_load): Ditto. (c86_4g_m7_sse_pinsr_reg): Ditto. (c86_4g_m7_sse_pinsr_reg_load): Ditto. (c86_4g_m7_avx_vpinsr_reg): Ditto. (c86_4g_m7_avx_vpinsr_reg_load): Ditto. (c86_4g_m7_avx512_perm_xmm): Ditto. (c86_4g_m7_avx512_perm_xmm_opload): Ditto. (c86_4g_m7_avx512_permi2_ymm): Ditto. (c86_4g_m7_avx512_permi2_zmm): Ditto. (c86_4g_m7_avx512_permi2_ymm_load): Ditto. (c86_4g_m7_avx512_permi2_zmm_load): Ditto. (c86_4g_m7_avx512_perm_zmm_imm): Ditto. (c86_4g_m7_avx512_perm_zmm_imm_load): Ditto. (c86_4g_m7_avx512_perm_zmm_noimm): Ditto. (c86_4g_m7_sse_perm_zmm_noimm_load): Ditto. (c86_4g_m7_avx512_insertx_ymm): Ditto. (c86_4g_m7_avx512_insertx_ymem): Ditto. (c86_4g_m7_avx512_insertx_zxmm): Ditto. (c86_4g_m7_avx512_insertx_zxmem): Ditto. (c86_4g_m7_avx512_insertx_zymm): Ditto. (c86_4g_m7_avx512_insertx_zymem): Ditto. (c86_4g_m7_avx_insertx_ymm): Ditto. (c86_4g_m7_avx_insertx_ymem): Ditto. (c86_4g_m7_avx512_shuf_xymm): Ditto. (c86_4g_m7_avx512_shuf_zmm): Ditto. (c86_4g_m7_avx512_shuf_xymem): Ditto. (c86_4g_m7_avx512_shuf_zmem): Ditto. (c86_4g_m7_sselogic_xymm): Ditto. (c86_4g_m7_sselogic_xymm_load): Ditto. (c86_4g_m7_avx512_cmpestr): Ditto. (c86_4g_m7_avx512_cmpestr_load): Ditto. (c86_4g_m7_avx512_log): Ditto. (c86_4g_m7_avx512_log_load): Ditto. (c86_4g_m7_avx512_vdbpsadbw_xymm): Ditto. (c86_4g_m7_avx512_vdbpsadbw_xymem): Ditto. (c86_4g_m7_avx512_vdbpsadbw_zmm): Ditto. (c86_4g_m7_avx512_vdbpsadbw_zmem): Ditto. (c86_4g_m7_avx512_abs): Ditto. (c86_4g_m7_avx512_abs_load): Ditto. (c86_4g_m7_avx_sign): Ditto. (c86_4g_m7_avx_sign_load): Ditto. (c86_4g_m7_avx_blend): Ditto. (c86_4g_m7_avx_blend_load): Ditto. (c86_4g_m7_avx512_aes): Ditto. (c86_4g_m7_avx512_aes_load): Ditto. (c86_4g_m7_avx_aes): Ditto. (c86_4g_m7_avx_aes_load): Ditto. (c86_4g_m7_extr): Ditto. (c86_4g_m7_extr_store): Ditto. (c86_4g_m7_avx_ssecomi_comi): Ditto. (c86_4g_m7_avx_ssecomi_comi_load): Ditto. (c86_4g_m7_avx_ssecomi_test): Ditto. (c86_4g_m7_avx_ssecomi_test_load): Ditto. (c86_4g_m7_avx512_imul): Ditto. (c86_4g_m7_avx512_imul_mem): Ditto. (c86_4g_m7_avx_imul): Ditto. (c86_4g_m7_avx_imul_mem): Ditto. (c86_4g_m7_avx512_mov_vmov): Ditto. (c86_4g_m7_avx512_mov_vmov_store): Ditto. (c86_4g_m7_avx512_mov_vmov_load): Ditto. (c86_4g_m7_avx512_vpmovx_y): Ditto. (c86_4g_m7_avx512_vpmovx_y_load): Ditto. (c86_4g_m7_avx512_vpmovx_z): Ditto. (c86_4g_m7_avx512_vpmovx_z_load): Ditto. (c86_4g_m7_avx512_vpmovx_x): Ditto. (c86_4g_m7_avx512_vpmovx_x_load): Ditto. (c86_4g_m7_avx_vpmovx_xx): Ditto. (c86_4g_m7_avx_vpmovx_xx_load): Ditto. (c86_4g_m7_avx512_expand): Ditto. (c86_4g_m7_avx512_expand_load): Ditto. (c86_4g_m7_avx512_expand_z): Ditto. (c86_4g_m7_avx512_expand_z_load): Ditto. (c86_4g_m7_avx512_movnt_load): Ditto. (c86_4g_m7_avx512_movnt_store): Ditto. (c86_4g_m7_sse_movnt_store): Ditto. (c86_4g_m7_sse_movnt): Ditto. (c86_4g_m7_avx512_blendv): Ditto. (c86_4g_m7_avx512_blendv_load): Ditto. (c86_4g_m7_sse_mov2): Ditto. (c86_4g_m7_sse_mov2_load): Ditto. (c86_4g_m7_avx512_sseishft_aligr): Ditto. (c86_4g_m7_avx512_sseishft_aligr_load): Ditto. (c86_4g_m7_avx512_sseishft_vshift): Ditto. (c86_4g_m7_avx512_sseishft_vshift_load): Ditto. (c86_4g_m7_avx512_sseadd_maxmin): Ditto. (c86_4g_m7_avx512_sseadd_maxmin_load): Ditto. (c86_4g_m7_avx_sseadd_maxmin): Ditto. (c86_4g_m7_avx_sseadd_maxmin_load): Ditto. (c86_4g_m7_sse_sseadd_maxmin): Ditto. (c86_4g_m7_sse_sseadd_maxmin_load): Ditto. (c86_4g_m7_avx512_sseadd): Ditto. (c86_4g_m7_avx512_sseadd_load): Ditto. (c86_4g_m7_avx_sseadd_hplus): Ditto. (c86_4g_m7_avx_sseadd_hplus_load): Ditto. (c86_4g_m7_avx512_sseiadd_madd): Ditto. (c86_4g_m7_avx512_sseiadd_madd_mem): Ditto. (c86_4g_m7_avx_sseiadd_sadbw): Ditto. (c86_4g_m7_avx_sseiadd_sadbw_mem): Ditto. (c86_4g_m7_sse_sseiadd_sadbw): Ditto. (c86_4g_m7_sse_sseiadd_sadbw_mem): Ditto. (c86_4g_m7_sse_sseiadd_madd): Ditto. (c86_4g_m7_sse_sseiadd_madd_mem): Ditto. (c86_4g_m7_avx512_sseiadd_avg): Ditto. (c86_4g_m7_avx512_sseiadd_avg_load): Ditto. (c86_4g_m7_avx_sseiadd_hplus): Ditto. (c86_4g_m7_avx_sseiadd_hplus_load): Ditto. (c86_4g_m7_sse_sseiadd_hplus): Ditto. (c86_4g_m7_sse_sseiadd_hplus_load): Ditto. (c86_4g_m8_avx512_ssemul): New reservation. (c86_4g_m8_avx512_ssemul_load): Ditto. (c86_4g_m7_avx512_ssediv_x): Add c86_4g_m8 to CPU attribute. (c86_4g_m7_avx512_ssediv_xmem): Ditto. (c86_4g_m7_avx512_ssediv_y): Ditto. (c86_4g_m7_avx512_ssediv_ymem): Ditto. (c86_4g_m7_avx512_ssediv_z): Ditto. (c86_4g_m7_avx512_ssediv_zmem): Ditto. (c86_4g_m7_avx512_ssecmp): Ditto. (c86_4g_m7_avx512_ssecmp_load): Ditto. (c86_4g_m7_avx512_ssecmp_z): Ditto. (c86_4g_m7_avx512_ssecmp_z_load): Ditto. (c86_4g_m7_avx512_ssecmp_vp): Ditto. (c86_4g_m7_avx512_ssecmp_vp_load): Ditto. (c86_4g_m7_avx512_ssecmp_vp_z): Ditto. (c86_4g_m7_avx512_ssecmp_vp_z_load): Ditto. (c86_4g_m7_avx_ssecmp_vp): Ditto. (c86_4g_m7_avx_ssecmp_vp_load): Ditto. (c86_4g_m7_avx512_ssecmp_test): Ditto. (c86_4g_m7_avx512_ssecmp_test_load): Ditto. (c86_4g_m7_avx512_ssecvt_xy): Ditto. (c86_4g_m7_avx512_ssecvt_xy_load): Ditto. (c86_4g_m7_avx512_ssecvt_y_z): Ditto. (c86_4g_m7_avx512_ssecvt_y_z_load): Ditto. (c86_4g_m7_avx512_ssecvt_z): Ditto. (c86_4g_m7_avx512_ssecvt_z_load): Ditto. (c86_4g_m7_avx_ssecvt): Ditto. (c86_4g_m7_avx_ssecvt_load): Ditto. (c86_4g_m7_sse_ssecvt_pspi): Ditto. (c86_4g_m7_sse_ssecvt_pspi_load): Ditto. (c86_4g_m7_sse_ssecvt_pi): Ditto. (c86_4g_m7_sse_ssecvt_pi_load): Ditto. (c86_4g_m8_avx512_muladd): New reservation. (c86_4g_m8_avx512_muladd_load): Ditto. (c86_4g_m7_avx512_muladd_madd): Add c86_4g_m8 to CPU attribute. (c86_4g_m7_avx512_muladd_madd_load): Ditto. (c86_4g_m7_avx512_sse_range): Ditto. (c86_4g_m7_avx512_sse_range_load): Ditto. (c86_4g_m7_avx512_sse_conflict_x): Ditto. (c86_4g_m7_avx512_sse_conflict_x_load): Ditto. (c86_4g_m7_avx512_sse_conflict_y): Ditto. (c86_4g_m7_avx512_sse_conflict_y_load): Ditto. (c86_4g_m7_avx512_sse_conflict_z): Ditto. (c86_4g_m7_avx512_sse_conflict_z_load): Ditto. (c86_4g_m7_avx512_sse_class): Ditto. (c86_4g_m7_avx512_sse_class_load): Ditto. (c86_4g_m7_avx512_sse_class_z): Ditto. (c86_4g_m7_avx512_sse_class_z_load): Ditto. (c86_4g_m7_avx_sse): Ditto. (c86_4g_m7_avx_sse_load): Ditto. (c86_4g_m7_avx512_sse_sqrt_sf_x): Ditto. (c86_4g_m7_avx512_sse_sqrt_sf_xload): Ditto. (c86_4g_m7_avx512_sse_sqrt_sf_y): Ditto. (c86_4g_m7_avx512_sse_sqrt_sf_yload): Ditto. (c86_4g_m7_avx512_sse_sqrt_sf_z): Ditto. (c86_4g_m7_avx512_sse_sqrt_sf_zload): Ditto. (c86_4g_m7_avx512_sse_sqrt_df_x): Ditto. (c86_4g_m7_avx512_sse_sqrt_df_xload): Ditto. (c86_4g_m7_avx512_sse_sqrt_df_y): Ditto. (c86_4g_m7_avx512_sse_sqrt_df_yload): Ditto. (c86_4g_m7_avx512_sse_sqrt_df_z): Ditto. (c86_4g_m7_avx512_sse_sqrt_df_zload): Ditto. (c86_4g_m7_avx512_msklog): Ditto. (c86_4g_m7_avx512_msklog_vector): Ditto. (c86_4g_m7_avx512_mskmov_reg_k): Ditto. (c86_4g_m7_avx512_mskmov_xy_k): Ditto. (c86_4g_m7_avx512_mskmov_z_k): Ditto. (c86_4g_m7_avx512_mskmov_k_k): Ditto. (c86_4g_m7_avx512_mskmov_k_reg): Ditto. (c86_4g_m7_avx512_mskmov_k_m): Ditto. * config/i386/driver-i386.cc (host_detect_local_cpu): Detect c86-4g-m8. * config/i386/i386-c.cc (ix86_target_macros_internal): Define c86-4g-m8 arch and tune macros. * config/i386/i386-options.cc (m_C86_4G_M8): New macro. (m_C86_4G): Include m_C86_4G_M8. (processor_cost_table): Add c86_4g_m8_cost. * config/i386/i386.cc (ix86_reassociation_width): Handle PROCESSOR_C86_4G_M8. * config/i386/i386.h (enum processor_type): Add PROCESSOR_C86_4G_M8. (PTA_C86_4G_M8): New. * config/i386/i386.md: Add c86_4g_m8 to cpu attribute. * config/i386/x86-tune-costs.h (c86_4g_m8_cost): New. * config/i386/x86-tune-sched.cc (ix86_issue_rate): Handle PROCESSOR_C86_4G_M8. (ix86_adjust_cost): Likewise. * config/i386/x86-tune.def (X86_TUNE_USE_SCATTER_2PARTS): Include m_C86_4G_M8. (X86_TUNE_USE_SCATTER_4PARTS): Likewise. (X86_TUNE_USE_SCATTER_8PARTS): Likewise. (X86_TUNE_SSE_REDUCTION_PREFER_PSHUF): Likewise. (X86_TUNE_AVX512_SPLIT_REGS): Likewise. (X86_TUNE_AVX512_MOVE_BY_PIECES): Likewise. (X86_TUNE_AVX512_MASKED_EPILOGUES): Likewise. * doc/extend.texi: Document c86-4g-m8 for __builtin_cpu_is. * doc/invoke.texi: Document c86-4g-m8. gcc/testsuite/ChangeLog: * g++.target/i386/mv33.C: Add c86-4g-m8 target clone test. * gcc.target/i386/funcspec-56.inc: Add c86-4g-m8 arch and tune target attribute tests. Signed-off-by: Xin Liu <[email protected]> (cherry picked from commit f06c1812ae7991e4aae8a3ff9d8920c31e4a1ac9) Diff: --- gcc/common/config/i386/cpuinfo.h | 6 + gcc/common/config/i386/i386-common.cc | 6 +- gcc/common/config/i386/i386-cpuinfo.h | 1 + gcc/config.gcc | 10 +- gcc/config/i386/{c86-4g-m7.md => c86-4g-m7m8.md} | 544 ++++++++++++----------- gcc/config/i386/driver-i386.cc | 7 +- gcc/config/i386/i386-c.cc | 7 + gcc/config/i386/i386-options.cc | 7 +- gcc/config/i386/i386.cc | 3 +- gcc/config/i386/i386.h | 2 + gcc/config/i386/i386.md | 4 +- gcc/config/i386/x86-tune-costs.h | 2 + gcc/config/i386/x86-tune-sched.cc | 2 + gcc/config/i386/x86-tune.def | 15 +- gcc/doc/extend.texi | 3 + gcc/doc/invoke.texi | 9 + gcc/testsuite/g++.target/i386/mv33.C | 6 + gcc/testsuite/gcc.target/i386/funcspec-56.inc | 2 + 18 files changed, 367 insertions(+), 269 deletions(-) diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index 62e9210b0675..f59090c8cdea 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -383,6 +383,12 @@ get_hygon_cpu (struct __processor_model *cpu_model, CHECK___builtin_cpu_is ("c86-4g-m7"); cpu_model->__cpu_subtype = HYGONFAM18H_C86_4G_M7; } + else if (model == 0x8) + { + cpu = "c86-4g-m8"; + CHECK___builtin_cpu_is ("c86-4g-m8"); + cpu_model->__cpu_subtype = HYGONFAM18H_C86_4G_M8; + } break; default: break; diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index 1dd9819c3091..effc570aca16 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -2208,7 +2208,8 @@ const char *const processor_names[] = "znver6", "c86-4g-m4", "c86-4g-m6", - "c86-4g-m7" + "c86-4g-m7", + "c86-4g-m8" }; /* Guarantee that the array is aligned with enum processor_type. */ @@ -2485,6 +2486,9 @@ const pta processor_alias_table[] = {"c86-4g-m7", PROCESSOR_C86_4G_M7, CPU_C86_4G_M7, PTA_C86_4G_M7, M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M7), P_PROC_AVX512F}, + {"c86-4g-m8", PROCESSOR_C86_4G_M8, CPU_C86_4G_M8, + PTA_C86_4G_M8, + M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M8), P_PROC_AVX512F}, {"generic", PROCESSOR_GENERIC, CPU_GENERIC, PTA_64BIT diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h index 5407d9d9ebaf..944b585dd57a 100644 --- a/gcc/common/config/i386/i386-cpuinfo.h +++ b/gcc/common/config/i386/i386-cpuinfo.h @@ -113,6 +113,7 @@ enum processor_subtypes HYGONFAM18H_C86_4G_M4, HYGONFAM18H_C86_4G_M6, HYGONFAM18H_C86_4G_M7, + HYGONFAM18H_C86_4G_M8, CPU_SUBTYPE_MAX }; diff --git a/gcc/config.gcc b/gcc/config.gcc index e7c8ea20f431..743421768ead 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -768,7 +768,7 @@ sapphirerapids alderlake rocketlake eden-x2 nano nano-1000 nano-2000 nano-3000 \ nano-x2 eden-x4 nano-x4 lujiazui yongfeng shijidadao x86-64 x86-64-v2 \ x86-64-v3 x86-64-v4 sierraforest graniterapids graniterapids-d grandridge \ arrowlake arrowlake-s clearwaterforest pantherlake diamondrapids novalake \ -c86-4g-m4 c86-4g-m6 c86-4g-m7 native" +c86-4g-m4 c86-4g-m6 c86-4g-m7 c86-4g-m8 native" # Additional x86 processors supported by --with-cpu=. Each processor # MUST be separated by exactly one space. @@ -4018,6 +4018,10 @@ case ${target} in arch=c86-4g-m7 cpu=c86-4g-m7 ;; + c86_4g_m8-*) + arch=c86-4g-m8 + cpu=c86-4g-m8 + ;; *) arch=pentiumpro cpu=generic @@ -4132,6 +4136,10 @@ case ${target} in arch=c86-4g-m7 cpu=c86-4g-m7 ;; + c86_4g_m8-*) + arch=c86-4g-m8 + cpu=c86-4g-m8 + ;; *) arch=x86-64 cpu=generic diff --git a/gcc/config/i386/c86-4g-m7.md b/gcc/config/i386/c86-4g-m7m8.md similarity index 84% rename from gcc/config/i386/c86-4g-m7.md rename to gcc/config/i386/c86-4g-m7m8.md index 19a8b356fa1b..e657c2fd03da 100644 --- a/gcc/config/i386/c86-4g-m7.md +++ b/gcc/config/i386/c86-4g-m7m8.md @@ -17,7 +17,7 @@ ;; <http://www.gnu.org/licenses/>. ;; -;; HYGON c86-4g-m7 Scheduling +;; HYGON c86-4g-m7/m8 Scheduling ;; Modeling automatons for decoders, integer execution pipes, ;; AGU pipes, branch, floating point execution, fp store units, ;; integer and floating point dividers. Split fpu1 and fpu3 @@ -112,15 +112,18 @@ (define_reservation "c86-4g-m7-fp1div1_fp3div3_x4x18" "(c86-4g-m7-fp1fdiv1x4,c86-4g-m7-fdiv1*18)|(c86-4g-m7-fp3fdiv3x4,c86-4g-m7-fdiv3*18)") ;; IMOV/IMOVX + +;; Some reservations keep the historical "m7" naming, while their CPU +;; attributes include both m7 and m8. (define_insn_reservation "c86_4g_m7_imov_xchg" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "imov") (and (eq_attr "c86_decode" "vector") (eq_attr "memory" "none")))) "c86-4g-m7-vector") (define_insn_reservation "c86_4g_m7_imov_xchg_load" 5 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "imov") (and (eq_attr "c86_decode" "vector") (eq_attr "memory" "!none")))) @@ -133,22 +136,29 @@ (eq_attr "memory" "none")))) "c86-4g-m7-direct,c86-4g-m7-ieu") +(define_insn_reservation "c86_4g_m8_imovx_cwde" 1 + (and (eq_attr "cpu" "c86_4g_m8") + (and (eq_attr "type" "imovx") + (and (eq_attr "c86_decode" "double") + (eq_attr "memory" "none")))) + "c86-4g-m7-direct,c86-4g-m7-ieu") + (define_insn_reservation "c86_4g_m7_imov" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "imov,imovx") (and (eq_attr "c86_decode" "direct") (eq_attr "memory" "none")))) "c86-4g-m7-direct,c86-4g-m7-ieu") (define_insn_reservation "c86_4g_m7_imov_load" 5 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "imov,imovx") (and (eq_attr "c86_decode" "!vector") (eq_attr "memory" "load")))) "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu") (define_insn_reservation "c86_4g_m7_imov_store" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "imov,imovx") (and (eq_attr "c86_decode" "!vector") (eq_attr "memory" "store")))) @@ -156,67 +166,67 @@ ;; PUSH (define_insn_reservation "c86_4g_m7_push" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "push,sse") (eq_attr "memory" "store"))) "c86-4g-m7-direct,c86-4g-m7-store") (define_insn_reservation "c86_4g_m7_push_mem" 5 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "push") (eq_attr "memory" "both"))) "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-store") ;; POP (define_insn_reservation "c86_4g_m7_pop" 4 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "pop") (eq_attr "memory" "load"))) "c86-4g-m7-direct,c86-4g-m7-load") (define_insn_reservation "c86_4g_m7_pop_mem" 5 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "pop") (eq_attr "memory" "both"))) "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store") ;; IMUL/IMULX (define_insn_reservation "c86_4g_m7_imul" 3 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "imul,imulx") (eq_attr "memory" "none"))) "c86-4g-m7-direct,c86-4g-m7-ieu1") (define_insn_reservation "c86_4g_m7_imul_load" 7 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "imul") (eq_attr "memory" "!none"))) "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu1") ;; IDIV (define_insn_reservation "c86_4g_m7_idiv" 7 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "idiv") (and (eq_attr "mode" "!QI") (eq_attr "memory" "none")))) "c86-4g-m7-double,c86-4g-m7-ieu3,c86-4g-m7-idiv*7") (define_insn_reservation "c86_4g_m7_idiv_QI" 6 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "idiv") (and (eq_attr "mode" "QI") (eq_attr "memory" "none")))) "c86-4g-m7-double,c86-4g-m7-ieu3,c86-4g-m7-idiv*6") (define_insn_reservation "c86_4g_m7_idiv_load" 11 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "idiv") (and (eq_attr "mode" "!QI") (eq_attr "memory" "load")))) "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3,c86-4g-m7-idiv*7") (define_insn_reservation "c86_4g_m7_idiv_QI_load" 10 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "idiv") (and (eq_attr "mode" "QI") (eq_attr "memory" "load")))) @@ -224,95 +234,95 @@ ;; Integer/genaral Instructions (define_insn_reservation "c86_4g_m7_insn" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "alu,negnot,rotate1,ishift1,test,incdec,icmp, rotate,rotatex,ishift,ishiftx,icmov") (eq_attr "memory" "none,unknown"))) "c86-4g-m7-direct,c86-4g-m7-ieu") (define_insn_reservation "c86_4g_m7_insn_load" 5 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "alu,incdec,icmp,test,ishift, ishiftx,icmov,rotate,rotatex") (eq_attr "memory" "load"))) "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu") (define_insn_reservation "c86_4g_m7_insn_store" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ishift1,rotate1,rotate,incdec, alu,icmov,ishift,negnot,alu1") (eq_attr "memory" "store"))) "c86-4g-m7-direct,c86-4g-m7-ieu,c86-4g-m7-store") (define_insn_reservation "c86_4g_m7_insn2_store" 5 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "icmp") (eq_attr "memory" "store"))) "c86-4g-m7-direct,c86-4g-m7-ieu,c86-4g-m7-store") (define_insn_reservation "c86_4g_m7_insn_both" 5 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "alu,negnot,rotate1,ishift1,incdec,rotate, rotatex,ishift,ishiftx,icmov") (eq_attr "memory" "both"))) "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu,c86-4g-m7-store") (define_insn_reservation "c86_4g_m7_setcc" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "setcc") (eq_attr "memory" "none,unknown"))) "c86-4g-m7-direct,c86-4g-m7-ieu0|c86-4g-m7-ieu3") (define_insn_reservation "c86_4g_m7_setcc_load" 5 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "setcc") (eq_attr "memory" "load"))) "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu0|c86-4g-m7-ieu3") (define_insn_reservation "c86_4g_m7_setcc_store" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "setcc") (eq_attr "memory" "store"))) "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-ieu0|c86-4g-m7-ieu3") ;; ALU1 (define_insn_reservation "c86_4g_m7_alu1_double" 2 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "alu1") (and (eq_attr "c86_decode" "double") (eq_attr "memory" "none,unknown")))) "c86-4g-m7-double,c86-4g-m7-ieu") (define_insn_reservation "c86_4g_m7_alu1_double_load" 6 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "alu1") (and (eq_attr "c86_decode" "double") (eq_attr "memory" "both")))) "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-ieu") (define_insn_reservation "c86_4g_m7_alu1_vector" 3 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "alu1") (and (eq_attr "c86_decode" "vector") (eq_attr "memory" "none,unknown")))) "c86-4g-m7-vector,c86-4g-m7-ivector*3") (define_insn_reservation "c86_4g_m7_alu1_vector_load" 7 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "alu1") (and (eq_attr "c86_decode" "vector") (eq_attr "memory" "both")))) "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-ivector*3") (define_insn_reservation "c86_4g_m7_alu1_direct" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "alu1") (and (eq_attr "c86_decode" "direct") (eq_attr "memory" "none,unknown")))) "c86-4g-m7-direct,c86-4g-m7-ieu") (define_insn_reservation "c86_4g_m7_alu1_direct_load" 5 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "alu1") (and (eq_attr "c86_decode" "direct") (eq_attr "memory" "both")))) @@ -320,58 +330,58 @@ ;; CALL/CALLV (define_insn_reservation "c86_4g_m7_call" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (eq_attr "type" "call,callv")) "c86-4g-m7-double,c86-4g-m7-store,c86-4g-m7-bru0") ;; IBR (define_insn_reservation "c86_4g_m7_branch" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ibr") (eq_attr "memory" "none"))) "c86-4g-m7-direct,c86-4g-m7-bru0") (define_insn_reservation "c86_4g_m7_branch_load" 5 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ibr") (eq_attr "memory" "load"))) "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-bru0") ;; LEA (define_insn_reservation "c86_4g_m7_lea" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (eq_attr "type" "lea")) "c86-4g-m7-direct,c86-4g-m7-ieu") ;; LEAVE (define_insn_reservation "c86_4g_m7_leave" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (eq_attr "type" "leave")) "c86-4g-m7-double,c86-4g-m7-ieu,c86-4g-m7-store") ;; STR (define_insn_reservation "c86_4g_m7_str" 3 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "str") (eq_attr "memory" "none"))) "c86-4g-m7-vector,c86-4g-m7-ivector*3") (define_insn_reservation "c86_4g_m7_str_load" 7 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "str") (eq_attr "memory" "load"))) "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-ivector*3") (define_insn_reservation "c86_4g_m7_ieu_vector" 5 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "other,multi") (and (eq_attr "unit" "!i387") (eq_attr "memory" "none,unknown")))) "c86-4g-m7-vector,c86-4g-m7-ivector*5") (define_insn_reservation "c86_4g_m7_ieu_vector_load" 9 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "other,multi") (and (eq_attr "unit" "!i387") (eq_attr "memory" "load")))) @@ -379,14 +389,14 @@ ;; SSEINS (define_insn_reservation "c86_4g_m7_sse_insertimm" 3 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseins") (and (eq_attr "memory" "none") (eq_attr "length_immediate" "2")))) "c86-4g-m7-double,c86-4g-m7-fpu_0_3,c86-4g-m7-fpu1") (define_insn_reservation "c86_4g_m7_sse_insert" 3 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseins") (and (eq_attr "memory" "none") (eq_attr "length_immediate" "!2")))) @@ -394,13 +404,13 @@ ;; FCMOV (define_insn_reservation "c86_4g_m7_fp_cmov" 4 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (eq_attr "type" "fcmov")) "c86-4g-m7-vector,c86-4g-m7-fvector*3") ;; FLD (define_insn_reservation "c86_4g_m7_fp_mov_direct_load" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "c86_decode" "direct") (and (eq_attr "type" "fmov") (eq_attr "memory" "load")))) @@ -408,7 +418,7 @@ ;; FST (define_insn_reservation "c86_4g_m7_fp_mov_direct_store" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "c86_decode" "direct") (and (eq_attr "type" "fmov") (eq_attr "memory" "store")))) @@ -416,7 +426,7 @@ ;; FILD (define_insn_reservation "c86_4g_m7_fp_mov_double_load" 11 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "c86_decode" "double") (and (eq_attr "type" "fmov") (eq_attr "memory" "load")))) @@ -424,14 +434,14 @@ ;; FIST (define_insn_reservation "c86_4g_m7_fp_mov_double_store" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "c86_decode" "double") (and (eq_attr "type" "fmov") (eq_attr "memory" "store")))) "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-store") (define_insn_reservation "c86_4g_m7_fp_mov_direct" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "c86_decode" "direct") (and (eq_attr "type" "fmov") (eq_attr "memory" "none")))) @@ -439,14 +449,14 @@ ;; FSQRT (define_insn_reservation "c86_4g_m7_fp_sqrt" 22 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "fpspc") (eq_attr "c86_attr" "sqrt"))) "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x18") ;; FPSPC (define_insn_reservation "c86_4g_m7_fp_spc_direct" 5 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "fpspc") (and (eq_attr "c86_decode" "direct") (and (eq_attr "c86_attr" "other") @@ -454,27 +464,27 @@ "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu3") (define_insn_reservation "c86_4g_m7_fp_spc" 6 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "fpspc") (and (eq_attr "c86_attr" "other") (eq_attr "memory" "none")))) "c86-4g-m7-vector,c86-4g-m7-fvector*6") (define_insn_reservation "c86_4g_m7_fp_op_mul" 5 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "fop,fmul") (eq_attr "memory" "none"))) "c86-4g-m7-direct,c86-4g-m7-fpu_0_2") (define_insn_reservation "c86_4g_m7_fp_op_mul_load" 12 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "fop,fmul") (and (eq_attr "fp_int_src" "false") (eq_attr "memory" "load")))) "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2") (define_insn_reservation "c86_4g_m7_fp_op_imul_load" 16 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "fmul") (and (eq_attr "fp_int_src" "true") (eq_attr "memory" "!none")))) @@ -482,98 +492,98 @@ ;; FDIV (define_insn_reservation "c86_4g_m7_fp_div" 15 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "fdiv") (eq_attr "memory" "none"))) "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x11") (define_insn_reservation "c86_4g_m7_fp_div_load" 22 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "fdiv") (and (eq_attr "fp_int_src" "false") (eq_attr "memory" "!none")))) "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp1div1_fp3div3_x4x11") (define_insn_reservation "c86_4g_m7_fp_idiv_load" 26 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "fdiv") (and (eq_attr "fp_int_src" "true") (eq_attr "memory" "!none")))) "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu1*4,c86-4g-m7-fp1div1_fp3div3_x4x11") (define_insn_reservation "c86_4g_m7_fp_fsgn" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (eq_attr "type" "fsgn")) "c86-4g-m7-direct,c86-4g-m7-fpu_1_3") ;; FCMP (define_insn_reservation "c86_4g_m7_fp_fcmp" 5 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "fcmp") (eq_attr "memory" "none"))) "c86-4g-m7-double,c86-4g-m7-fpu0,c86-4g-m7-fpu1") (define_insn_reservation "c86_4g_m7_fp_fcmp_load" 12 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "fcmp") (eq_attr "memory" "load"))) "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu0,c86-4g-m7-fpu1") ;; MMX (define_insn_reservation "c86_4g_m7_fp_mmx" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (eq_attr "type" "mmx")) "c86-4g-m7-direct") (define_insn_reservation "c86_4g_m7_mmx_add_cmp" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "mmxadd,mmxcmp") (eq_attr "memory" "none"))) "c86-4g-m7-direct,c86-4g-m7-fpu") (define_insn_reservation "c86_4g_m7_mmx_add_cmp_load" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "mmxadd,mmxcmp") (eq_attr "memory" "load"))) "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu") (define_insn_reservation "c86_4g_m7_mmx_cvt" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "mmxcvt") (and (eq_attr "c86_attr" "other") (eq_attr "memory" "none")))) "c86-4g-m7-direct,c86-4g-m7-fpu_0_1") (define_insn_reservation "c86_4g_m7_mmx_cvt_load" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "mmxcvt") (and (eq_attr "c86_attr" "other") (eq_attr "memory" "load")))) "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1") (define_insn_reservation "c86_4g_m7_mmx_shift" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "mmxshft") (and (eq_attr "c86_attr" "other") (eq_attr "memory" "none")))) "c86-4g-m7-direct,c86-4g-m7-fpu1") (define_insn_reservation "c86_4g_m7_mmx_shift_load" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "mmxshft") (and (eq_attr "c86_attr" "other") (eq_attr "memory" "load")))) "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1") (define_insn_reservation "c86_4g_m7_mmx_shift_avg" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "mmxshft") (and (eq_attr "c86_attr" "avg") (eq_attr "memory" "none")))) "c86-4g-m7-direct,c86-4g-m7-fpu") (define_insn_reservation "c86_4g_m7_mmx_shift_avg_load" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "mmxshft") (and (eq_attr "c86_attr" "avg") (eq_attr "memory" "load")))) @@ -581,53 +591,53 @@ ;; SADBW (define_insn_reservation "c86_4g_m7_mmx_shift_sadbw" 3 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "mmxshft") (and (eq_attr "c86_attr" "sadbw") (eq_attr "memory" "none")))) "c86-4g-m7-direct,c86-4g-m7-fpu0") (define_insn_reservation "c86_4g_m7_mmx_shift_sadbw_load" 10 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "mmxshft") (and (eq_attr "c86_attr" "sadbw") (eq_attr "memory" "load")))) "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0") (define_insn_reservation "c86_4g_m7_mmx_mov" 4 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "mmxmov") (eq_attr "memory" "none"))) "c86-4g-m7-direct,c86-4g-m7-fpu1") (define_insn_reservation "c86_4g_m7_mmx_mov_store" 4 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "mmxmov") (and (eq_attr "c86_attr" "other") (eq_attr "memory" "store")))) "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1") (define_insn_reservation "c86_4g_m7_mmx_mov_load" 11 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "mmxmov") (eq_attr "memory" "load"))) "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1") (define_insn_reservation "c86_4g_m7_mmx_mul" 3 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "mmxmul") (eq_attr "memory" "none"))) "c86-4g-m7-direct,c86-4g-m7-fpu0") (define_insn_reservation "c86_4g_m7_mmx_mul_load" 10 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "mmxmul") (eq_attr "memory" "load"))) "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0") ;; PINSR (define_insn_reservation "c86_4g_m7_sse_pinsr_reg" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog,mmxcvt") (and (eq_attr "c86_attr" "insr") (and (eq_attr "prefix" "orig") @@ -635,7 +645,7 @@ "c86-4g-m7-direct,c86-4g-m7-fpu") (define_insn_reservation "c86_4g_m7_sse_pinsr_reg_load" 3 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog,mmxcvt") (and (eq_attr "c86_attr" "insr") (and (eq_attr "prefix" "orig") @@ -643,7 +653,7 @@ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu") (define_insn_reservation "c86_4g_m7_avx_vpinsr_reg" 2 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog") (and (eq_attr "c86_attr" "insr") (and (eq_attr "prefix" "!orig") @@ -651,7 +661,7 @@ "c86-4g-m7-double,c86-4g-m7-fpu_1_3x2") (define_insn_reservation "c86_4g_m7_avx_vpinsr_reg_load" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog") (and (eq_attr "c86_attr" "insr") (and (eq_attr "prefix" "!orig") @@ -660,7 +670,7 @@ ;; PERM (define_insn_reservation "c86_4g_m7_avx512_perm_xmm" 3 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog") (and (ior (and (eq_attr "c86_attr" "perm2") (eq_attr "mode" "V4SF,V2DF,TI")) @@ -670,7 +680,7 @@ "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2") (define_insn_reservation "c86_4g_m7_avx512_perm_xmm_opload" 10 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog") (and (ior (and (eq_attr "c86_attr" "perm2") (eq_attr "mode" "V4SF,V2DF,TI")) @@ -680,7 +690,7 @@ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2") (define_insn_reservation "c86_4g_m7_avx512_permi2_ymm" 4 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog") (and (eq_attr "c86_attr" "perm2") (and (eq_attr "mode" "V8SF,V4DF,OI") @@ -688,7 +698,7 @@ "c86-4g-m7-vector,c86-4g-m7-fpux4") (define_insn_reservation "c86_4g_m7_avx512_permi2_zmm" 16 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog") (and (eq_attr "c86_attr" "perm2") (and (eq_attr "mode" "V16SF,V8DF,XI") @@ -696,7 +706,7 @@ "c86-4g-m7-vector,c86-4g-m7-fpux16") (define_insn_reservation "c86_4g_m7_avx512_permi2_ymm_load" 11 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog") (and (eq_attr "c86_attr" "perm2") (and (eq_attr "mode" "V8SF,V4DF,OI") @@ -704,7 +714,7 @@ "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux4") (define_insn_reservation "c86_4g_m7_avx512_permi2_zmm_load" 23 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog") (and (eq_attr "c86_attr" "perm2") (and (eq_attr "mode" "V16SF,V8DF,XI") @@ -712,7 +722,7 @@ "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux16") (define_insn_reservation "c86_4g_m7_avx512_perm_zmm_imm" 4 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog") (and (eq_attr "c86_attr" "perm") (and (eq_attr "mode" "V16SF,V8DF,XI") @@ -721,7 +731,7 @@ "c86-4g-m7-direct,c86-4g-m7-fpux4") (define_insn_reservation "c86_4g_m7_avx512_perm_zmm_imm_load" 11 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog") (and (eq_attr "c86_attr" "perm") (and (eq_attr "mode" "V16SF,V8DF,XI") @@ -730,7 +740,7 @@ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpux4") (define_insn_reservation "c86_4g_m7_avx512_perm_zmm_noimm" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog") (and (eq_attr "c86_attr" "perm") (and (eq_attr "mode" "V16SF,V8DF,XI") @@ -739,7 +749,7 @@ "c86-4g-m7-vector,c86-4g-m7-fpux8") (define_insn_reservation "c86_4g_m7_sse_perm_zmm_noimm_load" 15 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog") (and (eq_attr "c86_attr" "perm") (and (eq_attr "mode" "V16SF,V8DF,XI") @@ -749,7 +759,7 @@ ;; VINSERT (define_insn_reservation "c86_4g_m7_avx512_insertx_ymm" 3 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog,sselog1") (and (eq_attr "c86_attr" "insertx") (and (eq_attr "mode" "V8SF,V4DF,OI") @@ -758,7 +768,7 @@ "c86-4g-m7-direct,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_0_2") (define_insn_reservation "c86_4g_m7_avx512_insertx_ymem" 10 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog,sselog1") (and (eq_attr "c86_attr" "insertx") (and (eq_attr "mode" "V8SF,V4DF,OI") @@ -767,7 +777,7 @@ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_0_2") (define_insn_reservation "c86_4g_m7_avx512_insertx_zxmm" 5 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog") (and (eq_attr "c86_attr" "insertx") (and (eq_attr "mode" "V16SF,V8DF,XI") @@ -776,7 +786,7 @@ "c86-4g-m7-double,c86-4g-m7-fpu_0_2x2,c86-4g-m7-fpu_0_2x2") (define_insn_reservation "c86_4g_m7_avx512_insertx_zxmem" 12 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog") (and (eq_attr "c86_attr" "insertx") (and (eq_attr "mode" "V16SF,V8DF,XI") @@ -785,7 +795,7 @@ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2,c86-4g-m7-fpu_0_2x2") (define_insn_reservation "c86_4g_m7_avx512_insertx_zymm" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog") (and (eq_attr "c86_attr" "insertx") (and (eq_attr "mode" "V16SF,V8DF,XI") @@ -794,7 +804,7 @@ "c86-4g-m7-double,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_insertx_zymem" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog") (and (eq_attr "c86_attr" "insertx") (and (eq_attr "mode" "V16SF,V8DF,XI") @@ -803,7 +813,7 @@ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx_insertx_ymm" 3 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog,sselog1") (and (eq_attr "c86_attr" "insertx") (and (eq_attr "prefix" "!evex") @@ -811,7 +821,7 @@ "c86-4g-m7-direct,c86-4g-m7-fpu0*2") (define_insn_reservation "c86_4g_m7_avx_insertx_ymem" 10 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog,sselog1") (and (eq_attr "c86_attr" "insertx") (and (eq_attr "prefix" "!evex") @@ -820,7 +830,7 @@ ;; SHUF/MULTISHIFTQB (define_insn_reservation "c86_4g_m7_avx512_shuf_xymm" 3 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog") (and (eq_attr "c86_attr" "shufx") (and (not (eq_attr "mode" "V8DF,V16SF,XI")) @@ -828,7 +838,7 @@ "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2") (define_insn_reservation "c86_4g_m7_avx512_shuf_zmm" 4 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog") (and (eq_attr "c86_attr" "shufx") (and (eq_attr "mode" "V8DF,V16SF,XI") @@ -836,7 +846,7 @@ "c86-4g-m7-vector,c86-4g-m7-fpu_0_2x4") (define_insn_reservation "c86_4g_m7_avx512_shuf_xymem" 10 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog") (and (eq_attr "c86_attr" "shufx") (and (not (eq_attr "mode" "V8DF,V16SF,XI")) @@ -844,7 +854,7 @@ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2") (define_insn_reservation "c86_4g_m7_avx512_shuf_zmem" 11 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog") (and (eq_attr "c86_attr" "shufx") (and (eq_attr "mode" "V8DF,V16SF,XI") @@ -853,14 +863,14 @@ ;; SSELOGIC (define_insn_reservation "c86_4g_m7_sselogic_xymm" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog,sselog1") (and (eq_attr "c86_attr" "sselogic") (eq_attr "memory" "none")))) "c86-4g-m7-direct,c86-4g-m7-fpu") (define_insn_reservation "c86_4g_m7_sselogic_xymm_load" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog,sselog1") (and (eq_attr "c86_attr" "sselogic") (eq_attr "memory" "load")))) @@ -868,14 +878,14 @@ ;; CMPESTR (define_insn_reservation "c86_4g_m7_avx512_cmpestr" 6 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog") (and (eq_attr "c86_attr" "cmpestr") (eq_attr "memory" "none")))) "c86-4g-m7-vector,c86-4g-m7-fpux6") (define_insn_reservation "c86_4g_m7_avx512_cmpestr_load" 13 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog") (and (eq_attr "c86_attr" "cmpestr") (eq_attr "memory" "load")))) @@ -883,14 +893,14 @@ ;; SSELOG (define_insn_reservation "c86_4g_m7_avx512_log" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1") (and (eq_attr "c86_attr" "other") (eq_attr "memory" "none")))) "c86-4g-m7-direct,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_log_load" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1") (and (eq_attr "c86_attr" "other") (eq_attr "memory" "load")))) @@ -899,7 +909,7 @@ ;; SSELOG1 ;; VDBPSADBW (define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_xymm" 4 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog1") (and (eq_attr "c86_attr" "sadbw") (and (eq_attr "mode" "OI,TI") @@ -907,7 +917,7 @@ "c86-4g-m7-double,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_xymem" 11 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog1") (and (eq_attr "c86_attr" "sadbw") (and (eq_attr "mode" "OI,TI") @@ -915,7 +925,7 @@ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_zmm" 4 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog1") (and (eq_attr "c86_attr" "sadbw") (and (eq_attr "mode" "XI") @@ -923,7 +933,7 @@ "c86-4g-m7-vector,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3x2") (define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_zmem" 11 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog1") (and (eq_attr "c86_attr" "sadbw") (and (eq_attr "mode" "XI") @@ -932,7 +942,7 @@ ;; ABS (define_insn_reservation "c86_4g_m7_avx512_abs" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog1,sse") (and (eq_attr "c86_attr" "abs") (and (eq_attr "prefix" "evex") @@ -940,7 +950,7 @@ "c86-4g-m7-direct,c86-4g-m7-fpu") (define_insn_reservation "c86_4g_m7_avx512_abs_load" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog1,sse") (and (eq_attr "c86_attr" "abs") (and (eq_attr "prefix" "evex") @@ -949,14 +959,14 @@ ;; SIGN (define_insn_reservation "c86_4g_m7_avx_sign" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog1") (and (eq_attr "c86_attr" "sign") (eq_attr "memory" "none")))) "c86-4g-m7-direct,c86-4g-m7-fpu_0_3") (define_insn_reservation "c86_4g_m7_avx_sign_load" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog1") (and (eq_attr "c86_attr" "sign") (eq_attr "memory" "!none")))) @@ -964,7 +974,7 @@ ;; BLEND/ABS/AES (define_insn_reservation "c86_4g_m7_avx_blend" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog1") (and (eq_attr "c86_attr" "abs,blend,aes") (and (eq_attr "prefix" "!evex") @@ -972,7 +982,7 @@ "c86-4g-m7-direct,c86-4g-m7-fpu_0_1") (define_insn_reservation "c86_4g_m7_avx_blend_load" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog1") (and (eq_attr "c86_attr" "abs,blend,aes") (and (eq_attr "prefix" "!evex") @@ -980,7 +990,7 @@ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1") (define_insn_reservation "c86_4g_m7_avx512_aes" 3 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog1,ssecvt,sse") (and (eq_attr "c86_attr" "aes") (and (eq_attr "prefix" "evex") @@ -988,7 +998,7 @@ "c86-4g-m7-direct,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_aes_load" 10 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog1,ssecvt,sse") (and (eq_attr "c86_attr" "aes") (and (eq_attr "prefix" "evex") @@ -996,7 +1006,7 @@ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx_aes" 3 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog1") (and (eq_attr "c86_attr" "aes") (and (eq_attr "prefix" "!evex") @@ -1004,7 +1014,7 @@ "c86-4g-m7-direct,c86-4g-m7-fpu_0_1") (define_insn_reservation "c86_4g_m7_avx_aes_load" 10 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog1") (and (eq_attr "c86_attr" "aes") (and (eq_attr "prefix" "!evex") @@ -1013,14 +1023,14 @@ ;; EXTR (define_insn_reservation "c86_4g_m7_extr" 5 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog1,sselog,mmxcvt") (and (eq_attr "c86_attr" "extr") (eq_attr "memory" "none")))) "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1") (define_insn_reservation "c86_4g_m7_extr_store" 12 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sselog1,sselog,mmxcvt") (and (eq_attr "c86_attr" "extr") (eq_attr "memory" "store")))) @@ -1028,28 +1038,28 @@ ;; SSECOMI (define_insn_reservation "c86_4g_m7_avx_ssecomi_comi" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssecomi") (and (eq_attr "prefix_extra" "0") (eq_attr "memory" "none")))) "c86-4g-m7-double,c86-4g-m7-fpu") (define_insn_reservation "c86_4g_m7_avx_ssecomi_comi_load" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssecomi") (and (eq_attr "prefix_extra" "0") (eq_attr "memory" "load")))) "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu") (define_insn_reservation "c86_4g_m7_avx_ssecomi_test" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssecomi") (and (eq_attr "prefix_extra" "1") (eq_attr "memory" "none")))) "c86-4g-m7-direct,c86-4g-m7-fpu1|c86-4g-m7-fpu2") (define_insn_reservation "c86_4g_m7_avx_ssecomi_test_load" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssecomi") (and (eq_attr "prefix_extra" "1") (eq_attr "memory" "load")))) @@ -1057,28 +1067,28 @@ ;; SSEIMUL (define_insn_reservation "c86_4g_m7_avx512_imul" 3 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseimul") (and (eq_attr "prefix" "evex") (eq_attr "memory" "none")))) "c86-4g-m7-direct,c86-4g-m7-fpu_0_2") (define_insn_reservation "c86_4g_m7_avx512_imul_mem" 10 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseimul") (and (eq_attr "prefix" "evex") (eq_attr "memory" "load")))) "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2") (define_insn_reservation "c86_4g_m7_avx_imul" 3 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseimul") (and (eq_attr "prefix" "!evex") (eq_attr "memory" "none")))) "c86-4g-m7-direct,c86-4g-m7-fpu_0_3") (define_insn_reservation "c86_4g_m7_avx_imul_mem" 10 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseimul") (and (eq_attr "prefix" "!evex") (eq_attr "memory" "load")))) @@ -1086,28 +1096,28 @@ ;; SSEMOV (define_insn_reservation "c86_4g_m7_avx512_mov_vmov" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssemov,sseiadd") (and (eq_attr "c86_attr" "other,blend,maxmin") (eq_attr "memory" "none")))) "c86-4g-m7-direct,c86-4g-m7-fpu") (define_insn_reservation "c86_4g_m7_avx512_mov_vmov_store" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssemov") (and (eq_attr "c86_attr" "other") - (eq_attr "memory" "store")))) + (eq_attr "memory" "store")))) "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1") (define_insn_reservation "c86_4g_m7_avx512_mov_vmov_load" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssemov,sseiadd") (and (eq_attr "c86_attr" "other,blend,maxmin") (eq_attr "memory" "load")))) "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu") (define_insn_reservation "c86_4g_m7_avx512_vpmovx_y" 3 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssemov") (and (eq_attr "c86_attr" "vpmovx") (and (eq_attr "prefix" "evex") @@ -1116,7 +1126,7 @@ "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2") (define_insn_reservation "c86_4g_m7_avx512_vpmovx_y_load" 10 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssemov,sselog1") (and (eq_attr "c86_attr" "vpmovx") (and (eq_attr "prefix" "evex") @@ -1125,7 +1135,7 @@ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-fpu_0_2x2") (define_insn_reservation "c86_4g_m7_avx512_vpmovx_z" 5 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssemov") (and (eq_attr "c86_attr" "vpmovx") (and (eq_attr "mode" "XI") @@ -1133,7 +1143,7 @@ "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x4") (define_insn_reservation "c86_4g_m7_avx512_vpmovx_z_load" 12 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssemov") (and (eq_attr "c86_attr" "vpmovx") (and (eq_attr "mode" "XI") @@ -1141,7 +1151,7 @@ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x4") (define_insn_reservation "c86_4g_m7_avx512_vpmovx_x" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssemov") (and (eq_attr "c86_attr" "vpmovx") (and (eq_attr "prefix" "evex") @@ -1150,7 +1160,7 @@ "c86-4g-m7-direct,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_vpmovx_x_load" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssemov") (and (eq_attr "c86_attr" "vpmovx") (and (eq_attr "prefix" "evex") @@ -1159,7 +1169,7 @@ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx_vpmovx_xx" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssemov") (and (eq_attr "c86_attr" "vpmovx") (and (eq_attr "prefix" "!evex") @@ -1167,7 +1177,7 @@ "c86-4g-m7-direct,c86-4g-m7-fpu1|c86-4g-m7-fpu2") (define_insn_reservation "c86_4g_m7_avx_vpmovx_xx_load" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssemov") (and (eq_attr "c86_attr" "vpmovx") (and (eq_attr "prefix" "!evex") @@ -1176,7 +1186,7 @@ ;; EXPAND (define_insn_reservation "c86_4g_m7_avx512_expand" 3 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssemov") (and (eq_attr "c86_attr" "expand,compress") (and (not (eq_attr "mode" "XI,V16SF,V8DF")) @@ -1184,7 +1194,7 @@ "c86-4g-m7-direct,c86-4g-m7-fpu3,c86-4g-m7-fpu_0_3") (define_insn_reservation "c86_4g_m7_avx512_expand_load" 10 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssemov") (and (eq_attr "c86_attr" "expand,compress") (and (not (eq_attr "mode" "XI,V16SF,V8DF")) @@ -1192,7 +1202,7 @@ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu3,c86-4g-m7-fpu_0_3") (define_insn_reservation "c86_4g_m7_avx512_expand_z" 10 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssemov") (and (eq_attr "c86_attr" "expand,compress") (and (eq_attr "mode" "XI,V16SF,V8DF") @@ -1200,7 +1210,7 @@ "c86-4g-m7-vector,c86-4g-m7-fpu3,c86-4g-m7-fpu_0_3") (define_insn_reservation "c86_4g_m7_avx512_expand_z_load" 17 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssemov") (and (eq_attr "c86_attr" "expand,compress") (and (eq_attr "mode" "XI,V16SF,V8DF") @@ -1209,7 +1219,7 @@ ;; MOVNT (define_insn_reservation "c86_4g_m7_avx512_movnt_load" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssemov") (and (eq_attr "c86_attr" "movnt") (and (eq_attr "mode" "XI,V16SF,V8DF") @@ -1217,7 +1227,7 @@ "c86-4g-m7-double,c86-4g-m7-load") (define_insn_reservation "c86_4g_m7_avx512_movnt_store" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssemov") (and (eq_attr "c86_attr" "movnt") (and (eq_attr "mode" "XI,V16SF,V8DF") @@ -1225,7 +1235,7 @@ "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1*2") (define_insn_reservation "c86_4g_m7_sse_movnt_store" 4 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssemov,mmxmov") (and (eq_attr "c86_attr" "movnt") (and (not (eq_attr "mode" "XI,V16SF,V8DF")) @@ -1233,7 +1243,7 @@ "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1") (define_insn_reservation "c86_4g_m7_sse_movnt" 4 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssemov") (and (eq_attr "c86_attr" "movnt") (and (not (eq_attr "mode" "XI,V16SF,V8DF")) @@ -1242,14 +1252,14 @@ ;; BLENDV (define_insn_reservation "c86_4g_m7_avx512_blendv" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssemov") (and (eq_attr "c86_attr" "blendv") (eq_attr "memory" "none")))) "c86-4g-m7-direct,c86-4g-m7-fpu_0_1") (define_insn_reservation "c86_4g_m7_avx512_blendv_load" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssemov") (and (eq_attr "c86_attr" "blendv") (eq_attr "memory" "load")))) @@ -1257,20 +1267,20 @@ ;; SSEMOV2 (define_insn_reservation "c86_4g_m7_sse_mov2" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssemov2") (eq_attr "memory" "none"))) "c86-4g-m7-direct,c86-4g-m7-fpu") (define_insn_reservation "c86_4g_m7_sse_mov2_load" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssemov2") (eq_attr "memory" "!none"))) "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu") ;; SSEISHFT (define_insn_reservation "c86_4g_m7_avx512_sseishft_aligr" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseishft") (and (eq_attr "prefix_extra" "1") (and (eq_attr "prefix" "evex") @@ -1278,7 +1288,7 @@ "c86-4g-m7-direct,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_sseishft_aligr_load" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseishft") (and (eq_attr "prefix_extra" "1") (and (eq_attr "prefix" "evex") @@ -1286,14 +1296,14 @@ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_sseishft_vshift" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseishft") (and (eq_attr "prefix_extra" "!1") (eq_attr "memory" "none")))) "c86-4g-m7-direct,c86-4g-m7-fpu_0_2") (define_insn_reservation "c86_4g_m7_avx512_sseishft_vshift_load" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseishft") (and (eq_attr "prefix_extra" "!1") (eq_attr "memory" "!none")))) @@ -1302,23 +1312,23 @@ ;; SSEADD (define_insn_reservation "c86_4g_m7_avx512_sseadd_maxmin" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseadd,sse") (and (eq_attr "c86_attr" "maxmin") (and (eq_attr "prefix" "evex") - (eq_attr "memory" "none"))))) + (eq_attr "memory" "none"))))) "c86-4g-m7-direct,c86-4g-m7-fpu_0_2") (define_insn_reservation "c86_4g_m7_avx512_sseadd_maxmin_load" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseadd,sse") (and (eq_attr "c86_attr" "maxmin") (and (eq_attr "prefix" "evex") - (eq_attr "memory" "load"))))) + (eq_attr "memory" "load"))))) "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2") (define_insn_reservation "c86_4g_m7_avx_sseadd_maxmin" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseadd,sse") (and (eq_attr "c86_attr" "maxmin") (and (eq_attr "prefix" "vex") @@ -1326,7 +1336,7 @@ "c86-4g-m7-direct,c86-4g-m7-fpu_0_1") (define_insn_reservation "c86_4g_m7_avx_sseadd_maxmin_load" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseadd,sse") (and (eq_attr "c86_attr" "maxmin") (and (eq_attr "prefix" "vex") @@ -1334,7 +1344,7 @@ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1") (define_insn_reservation "c86_4g_m7_sse_sseadd_maxmin" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseadd,sse") (and (eq_attr "c86_attr" "maxmin") (and (eq_attr "prefix" "orig") @@ -1342,7 +1352,7 @@ "c86-4g-m7-direct,c86-4g-m7-fpu2|c86-4g-m7-fpu3") (define_insn_reservation "c86_4g_m7_sse_sseadd_maxmin_load" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseadd,sse") (and (eq_attr "c86_attr" "maxmin") (and (eq_attr "prefix" "orig") @@ -1351,29 +1361,29 @@ ;; SUB/ADD (define_insn_reservation "c86_4g_m7_avx512_sseadd" 3 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseadd") (and (eq_attr "c86_attr" "other") - (eq_attr "memory" "none")))) + (eq_attr "memory" "none")))) "c86-4g-m7-direct,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_sseadd_load" 10 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseadd") (and (eq_attr "c86_attr" "other") - (eq_attr "memory" "load")))) + (eq_attr "memory" "load")))) "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3") ;; HADD/HSUB (define_insn_reservation "c86_4g_m7_avx_sseadd_hplus" 7 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseadd,sseadd1") (and (eq_attr "c86_attr" "hplus") (eq_attr "memory" "none")))) "c86-4g-m7-vector") (define_insn_reservation "c86_4g_m7_avx_sseadd_hplus_load" 14 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseadd,sseadd1") (and (eq_attr "c86_attr" "hplus") (eq_attr "memory" "load")))) @@ -1381,7 +1391,7 @@ ;; SSEIADD (define_insn_reservation "c86_4g_m7_avx512_sseiadd_madd" 3 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseiadd") (and (eq_attr "c86_attr" "sadbw,madd") (and (ior (eq_attr "prefix" "evex") @@ -1390,7 +1400,7 @@ "c86-4g-m7-direct,c86-4g-m7-fpu_0_2") (define_insn_reservation "c86_4g_m7_avx512_sseiadd_madd_mem" 10 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseiadd") (and (eq_attr "c86_attr" "sadbw,madd") (and (ior (eq_attr "prefix" "evex") @@ -1399,7 +1409,7 @@ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2") (define_insn_reservation "c86_4g_m7_avx_sseiadd_sadbw" 3 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseiadd") (and (eq_attr "c86_attr" "sadbw") (and (eq_attr "prefix" "vex,maybe_evex") @@ -1408,7 +1418,7 @@ "c86-4g-m7-direct,c86-4g-m7-fpu_0_1") (define_insn_reservation "c86_4g_m7_avx_sseiadd_sadbw_mem" 10 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseiadd") (and (eq_attr "c86_attr" "sadbw") (and (eq_attr "prefix" "vex,maybe_evex") @@ -1417,7 +1427,7 @@ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1") (define_insn_reservation "c86_4g_m7_sse_sseiadd_sadbw" 3 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseiadd") (and (eq_attr "c86_attr" "sadbw") (and (eq_attr "prefix" "orig") @@ -1425,7 +1435,7 @@ "c86-4g-m7-direct,c86-4g-m7-fpu_0_3") (define_insn_reservation "c86_4g_m7_sse_sseiadd_sadbw_mem" 10 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseiadd") (and (eq_attr "c86_attr" "sadbw") (and (eq_attr "prefix" "orig") @@ -1433,7 +1443,7 @@ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_3") (define_insn_reservation "c86_4g_m7_sse_sseiadd_madd" 3 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseiadd") (and (eq_attr "c86_attr" "madd") (and (eq_attr "prefix" "!evex") @@ -1441,7 +1451,7 @@ "c86-4g-m7-direct,c86-4g-m7-fpu0") (define_insn_reservation "c86_4g_m7_sse_sseiadd_madd_mem" 10 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseiadd") (and (eq_attr "c86_attr" "madd") (and (eq_attr "prefix" "!evex") @@ -1450,21 +1460,21 @@ ;; AVG (define_insn_reservation "c86_4g_m7_avx512_sseiadd_avg" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseiadd") (and (eq_attr "c86_attr" "avg") (eq_attr "memory" "none")))) "c86-4g-m7-direct,c86-4g-m7-fpu") (define_insn_reservation "c86_4g_m7_avx512_sseiadd_avg_load" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseiadd") (and (eq_attr "c86_attr" "avg") (eq_attr "memory" "load")))) "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu") (define_insn_reservation "c86_4g_m7_avx_sseiadd_hplus" 3 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseiadd,sseiadd1") (and (eq_attr "c86_attr" "hplus") (and (eq_attr "prefix" "vex") @@ -1472,7 +1482,7 @@ "c86-4g-m7-vector") (define_insn_reservation "c86_4g_m7_avx_sseiadd_hplus_load" 10 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseiadd,sseiadd1") (and (eq_attr "c86_attr" "hplus") (and (eq_attr "prefix" "vex") @@ -1480,15 +1490,15 @@ "c86-4g-m7-vector,c86-4g-m7-load") (define_insn_reservation "c86_4g_m7_sse_sseiadd_hplus" 3 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseiadd,sseiadd1") (and (eq_attr "c86_attr" "hplus") (and (eq_attr "prefix" "orig") - (eq_attr "memory" "none"))))) + (eq_attr "memory" "none"))))) "c86-4g-m7-vector,c86-4g-m7-fpux2") (define_insn_reservation "c86_4g_m7_sse_sseiadd_hplus_load" 10 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sseiadd,sseiadd1") (and (eq_attr "c86_attr" "hplus") (and (eq_attr "prefix" "orig") @@ -1508,44 +1518,56 @@ (eq_attr "memory" "load"))) "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2") +(define_insn_reservation "c86_4g_m8_avx512_ssemul" 4 + (and (eq_attr "cpu" "c86_4g_m8") + (and (eq_attr "type" "ssemul") + (eq_attr "memory" "none"))) + "c86-4g-m7-direct,c86-4g-m7-fpu_0_2") + +(define_insn_reservation "c86_4g_m8_avx512_ssemul_load" 11 + (and (eq_attr "cpu" "c86_4g_m8") + (and (eq_attr "type" "ssemul") + (eq_attr "memory" "load"))) + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2") + ;; SSEDIV (define_insn_reservation "c86_4g_m7_avx512_ssediv_x" 13 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssediv") (and (eq_attr "mode" "SF,DF,V4SF,V2DF") (eq_attr "memory" "none")))) "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x8") (define_insn_reservation "c86_4g_m7_avx512_ssediv_xmem" 20 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssediv") (and (eq_attr "mode" "SF,DF,V4SF,V2DF") (eq_attr "memory" "load")))) "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp1div1_fp3div3_x4x8") (define_insn_reservation "c86_4g_m7_avx512_ssediv_y" 13 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssediv") (and (eq_attr "mode" "V8SF,V4DF") (eq_attr "memory" "none")))) "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*8") (define_insn_reservation "c86_4g_m7_avx512_ssediv_ymem" 20 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssediv") (and (eq_attr "mode" "V8SF,V4DF") (eq_attr "memory" "load")))) "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*8") (define_insn_reservation "c86_4g_m7_avx512_ssediv_z" 24 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssediv") (and (eq_attr "mode" "V16SF,V8DF") (eq_attr "memory" "none")))) "c86-4g-m7-double,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*20") (define_insn_reservation "c86_4g_m7_avx512_ssediv_zmem" 31 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssediv") (and (eq_attr "mode" "V16SF,V8DF") (eq_attr "memory" "load")))) @@ -1553,7 +1575,7 @@ ;; SSECMP (define_insn_reservation "c86_4g_m7_avx512_ssecmp" 5 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssecmp") (and (eq_attr "prefix" "evex") (and (eq_attr "mode" "V2DF,V4DF,V8SF,V4SF,SF,DF") @@ -1561,7 +1583,7 @@ "c86-4g-m7-double,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_ssecmp_load" 12 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssecmp") (and (eq_attr "prefix" "evex") (and (eq_attr "mode" "V2DF,V4DF,V8SF,V4SF,SF,DF") @@ -1569,7 +1591,7 @@ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_ssecmp_z" 5 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssecmp") (and (eq_attr "mode" "V16SF,V8DF,XI") (and (eq_attr "c86_attr" "other") @@ -1577,7 +1599,7 @@ "c86-4g-m7-vector,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_ssecmp_z_load" 12 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssecmp") (and (eq_attr "mode" "V16SF,V8DF,XI") (and (eq_attr "c86_attr" "other") @@ -1585,7 +1607,7 @@ "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3x2") (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp" 5 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssecmp") (and (eq_attr "prefix" "evex") (and (eq_attr "mode" "TI,OI") @@ -1594,7 +1616,7 @@ "c86-4g-m7-double,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp_load" 12 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssecmp") (and (eq_attr "prefix" "evex") (and (eq_attr "mode" "TI,OI") @@ -1603,7 +1625,7 @@ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp_z" 5 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssecmp") (and (eq_attr "prefix" "evex") (and (eq_attr "mode" "XI") @@ -1612,7 +1634,7 @@ "c86-4g-m7-vector,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp_z_load" 12 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssecmp") (and (eq_attr "prefix" "evex") (and (eq_attr "mode" "XI") @@ -1621,14 +1643,14 @@ "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3x2") (define_insn_reservation "c86_4g_m7_avx_ssecmp_vp" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssecmp") (and (eq_attr "prefix" "!evex") (eq_attr "memory" "none")))) "c86-4g-m7-direct,c86-4g-m7-fpu") (define_insn_reservation "c86_4g_m7_avx_ssecmp_vp_load" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssecmp") (and (eq_attr "prefix" "!evex") (eq_attr "memory" "load")))) @@ -1636,7 +1658,7 @@ ;; VPTEST (define_insn_reservation "c86_4g_m7_avx512_ssecmp_test" 6 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssecmp") (and (eq_attr "mode" "TI,OI") (and (eq_attr "c86_attr" "ptest") @@ -1644,7 +1666,7 @@ "c86-4g-m7-double,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_ssecmp_test_load" 13 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssecmp") (and (eq_attr "mode" "TI,OI") (and (eq_attr "c86_attr" "ptest") @@ -1653,7 +1675,7 @@ ;; SSECVT (define_insn_reservation "c86_4g_m7_avx512_ssecvt_xy" 4 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssecvt") (and (eq_attr "c86_attr" "other") (and (eq_attr "prefix" "evex") @@ -1664,7 +1686,7 @@ "c86-4g-m7-direct,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_ssecvt_xy_load" 11 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssecvt") (and (eq_attr "prefix" "evex") (and (eq_attr "c86_attr" "other") @@ -1675,7 +1697,7 @@ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_ssecvt_y_z" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssecvt") (and (eq_attr "mode" "OI,V8SF,V4DF") (and (eq_attr "c86_attr" "other") @@ -1685,7 +1707,7 @@ "c86-4g-m7-double,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_ssecvt_y_z_load" 15 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssecvt") (and (eq_attr "mode" "OI,V8SF,V4DF") (and (eq_attr "c86_attr" "other") @@ -1695,7 +1717,7 @@ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_ssecvt_z" 4 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssecvt") (and (eq_attr "c86_attr" "other") (and (eq_attr "mode" "XI,V16SF,V8DF") @@ -1703,7 +1725,7 @@ "c86-4g-m7-double,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_ssecvt_z_load" 11 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssecvt") (and (eq_attr "c86_attr" "other") (and (eq_attr "mode" "XI,V16SF,V8DF") @@ -1711,7 +1733,7 @@ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx_ssecvt" 4 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssecvt") (and (eq_attr "prefix" "!evex") (and (eq_attr "mmx_isa" "base") @@ -1719,7 +1741,7 @@ "c86-4g-m7-direct,c86-4g-m7-fpu2|c86-4g-m7-fpu3") (define_insn_reservation "c86_4g_m7_avx_ssecvt_load" 11 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssecvt") (and (eq_attr "prefix" "!evex") (and (eq_attr "mmx_isa" "base") @@ -1728,21 +1750,21 @@ ;; CVTPI (define_insn_reservation "c86_4g_m7_sse_ssecvt_pspi" 4 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssecvt") (and (eq_attr "mode" "SF,DI") (eq_attr "memory" "none")))) "c86-4g-m7-direct,c86-4g-m7-fpu1") (define_insn_reservation "c86_4g_m7_sse_ssecvt_pspi_load" 11 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssecvt") (and (eq_attr "mode" "SF,DI") (eq_attr "memory" "load")))) "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1") (define_insn_reservation "c86_4g_m7_sse_ssecvt_pi" 5 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssecvt") (and (not (eq_attr "mode" "SF,DI")) (and (eq_attr "mmx_isa" "native") @@ -1750,7 +1772,7 @@ "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1") (define_insn_reservation "c86_4g_m7_sse_ssecvt_pi_load" 12 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssecvt") (and (not (eq_attr "mode" "SF,DI")) (and (eq_attr "mmx_isa" "native") @@ -1772,8 +1794,22 @@ (eq_attr "memory" "load")))) "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2") +(define_insn_reservation "c86_4g_m8_avx512_muladd" 5 + (and (eq_attr "cpu" "c86_4g_m8") + (and (eq_attr "type" "ssemuladd") + (and (eq_attr "c86_attr" "other") + (eq_attr "memory" "none")))) + "c86-4g-m7-direct,c86-4g-m7-fpu_0_2") + +(define_insn_reservation "c86_4g_m8_avx512_muladd_load" 12 + (and (eq_attr "cpu" "c86_4g_m8") + (and (eq_attr "type" "ssemuladd") + (and (eq_attr "c86_attr" "other") + (eq_attr "memory" "load")))) + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2") + (define_insn_reservation "c86_4g_m7_avx512_muladd_madd" 4 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssemuladd,sse") (and (eq_attr "c86_attr" "madd,rcp") (and (eq_attr "prefix" "evex") @@ -1781,7 +1817,7 @@ "c86-4g-m7-direct,c86-4g-m7-fpu_0_2") (define_insn_reservation "c86_4g_m7_avx512_muladd_madd_load" 11 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "ssemuladd,sse") (and (eq_attr "c86_attr" "madd,rcp") (and (eq_attr "prefix" "evex") @@ -1790,7 +1826,7 @@ ;; SSE (define_insn_reservation "c86_4g_m7_avx512_sse_range" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sse") (and (eq_attr "c86_attr" "other") (and (eq_attr "length_immediate" "!1") @@ -1800,7 +1836,7 @@ "c86-4g-m7-direct,c86-4g-m7-fpu_0_2") (define_insn_reservation "c86_4g_m7_avx512_sse_range_load" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sse") (and (eq_attr "c86_attr" "other") (and (eq_attr "length_immediate" "!1") @@ -1810,7 +1846,7 @@ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2") (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_x" 2 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sse") (and (eq_attr "c86_decode" "vector") (and (eq_attr "mode" "TI") @@ -1818,7 +1854,7 @@ "c86-4g-m7-vector,c86-4g-m7-fpu_1_3x2") (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_x_load" 9 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sse") (and (eq_attr "c86_decode" "vector") (and (eq_attr "mode" "TI") @@ -1826,7 +1862,7 @@ "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_1_3x2") (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_y" 5 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sse") (and (eq_attr "c86_decode" "vector") (and (eq_attr "mode" "OI") @@ -1834,7 +1870,7 @@ "c86-4g-m7-vector,c86-4g-m7-fpu_1_3x3") (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_y_load" 12 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sse") (and (eq_attr "c86_decode" "vector") (and (eq_attr "mode" "OI") @@ -1842,7 +1878,7 @@ "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_1_3x3") (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_z" 8 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sse") (and (eq_attr "c86_decode" "vector") (and (eq_attr "mode" "XI") @@ -1850,7 +1886,7 @@ "c86-4g-m7-vector,c86-4g-m7-fpu_1_3x6") (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_z_load" 15 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sse") (and (eq_attr "c86_decode" "vector") (and (eq_attr "mode" "XI") @@ -1858,7 +1894,7 @@ "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_1_3x6") (define_insn_reservation "c86_4g_m7_avx512_sse_class" 4 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sse") (and (eq_attr "c86_attr" "other") (and (eq_attr "length_immediate" "1") @@ -1867,7 +1903,7 @@ "c86-4g-m7-double,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_sse_class_load" 11 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sse") (and (eq_attr "c86_attr" "other") (and (eq_attr "length_immediate" "1") @@ -1876,7 +1912,7 @@ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_sse_class_z" 4 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sse") (and (eq_attr "c86_attr" "other") (and (eq_attr "length_immediate" "1") @@ -1885,7 +1921,7 @@ "c86-4g-m7-vector,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_sse_class_z_load" 11 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sse") (and (eq_attr "c86_attr" "other") (and (eq_attr "length_immediate" "1") @@ -1894,7 +1930,7 @@ "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx_sse" 5 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sse") (and (eq_attr "c86_attr" "rcp,other") (and (eq_attr "prefix" "!evex") @@ -1902,7 +1938,7 @@ "c86-4g-m7-direct,c86-4g-m7-fpu_0_1") (define_insn_reservation "c86_4g_m7_avx_sse_load" 12 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sse") (and (eq_attr "c86_attr" "rcp,other") (and (eq_attr "prefix" "!evex") @@ -1911,7 +1947,7 @@ ;; SSE SQRT (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_x" 14 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sse") (and (eq_attr "mode" "SF,V4SF") (and (eq_attr "c86_attr" "sqrt") @@ -1919,7 +1955,7 @@ "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x9") (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_xload" 21 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sse") (and (eq_attr "mode" "SF,V4SF") (and (eq_attr "c86_attr" "sqrt") @@ -1927,7 +1963,7 @@ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp1div1_fp3div3_x4x9") (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_y" 14 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sse") (and (eq_attr "mode" "V8SF") (and (eq_attr "c86_attr" "sqrt") @@ -1935,7 +1971,7 @@ "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*9") (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_yload" 21 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sse") (and (eq_attr "mode" "V8SF") (and (eq_attr "c86_attr" "sqrt") @@ -1943,7 +1979,7 @@ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*9") (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_z" 26 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sse") (and (eq_attr "mode" "V16SF") (and (eq_attr "c86_attr" "sqrt") @@ -1951,7 +1987,7 @@ "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*22") (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_zload" 33 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sse") (and (eq_attr "mode" "V16SF") (and (eq_attr "c86_attr" "sqrt") @@ -1959,7 +1995,7 @@ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*22") (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_x" 20 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sse") (and (eq_attr "mode" "DF,V2DF") (and (eq_attr "c86_attr" "sqrt") @@ -1967,7 +2003,7 @@ "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x15") (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_xload" 27 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sse") (and (eq_attr "mode" "DF,V2DF") (and (eq_attr "c86_attr" "sqrt") @@ -1975,7 +2011,7 @@ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp1div1_fp3div3_x4x15") (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_y" 20 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sse") (and (eq_attr "mode" "V4DF") (and (eq_attr "c86_attr" "sqrt") @@ -1983,7 +2019,7 @@ "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*15") (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_yload" 27 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sse") (and (eq_attr "mode" "V4DF") (and (eq_attr "c86_attr" "sqrt") @@ -1991,7 +2027,7 @@ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*15") (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_z" 38 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sse") (and (eq_attr "mode" "V8DF") (and (eq_attr "c86_attr" "sqrt") @@ -1999,7 +2035,7 @@ "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*34") (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_zload" 45 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "sse") (and (eq_attr "mode" "V8DF") (and (eq_attr "c86_attr" "sqrt") @@ -2008,53 +2044,53 @@ ;; MSKLOG/MSKMOV (define_insn_reservation "c86_4g_m7_avx512_msklog" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "msklog") (eq_attr "c86_decode" "direct"))) "c86-4g-m7-direct,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_msklog_vector" 4 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "msklog") (eq_attr "c86_decode" "vector"))) "c86-4g-m7-vector,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_mskmov_reg_k" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "mskmov") (and (match_operand 0 "register_operand" "r") (eq_attr "memory" "none")))) "c86-4g-m7-double,c86-4g-m7-fpu3,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_mskmov_xy_k" 2 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "mskmov") (ior (match_operand:V2DI 0 "register_operand" "v") (match_operand:V4DI 0 "register_operand" "v")))) "c86-4g-m7-double,c86-4g-m7-fpu3,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_mskmov_z_k" 3 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "mskmov") (match_operand:V8DI 0 "register_operand" "v"))) "c86-4g-m7-vector,c86-4g-m7-fpu3,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_mskmov_k_k" 1 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "mskmov") (and (match_operand 0 "register_operand" "k") (match_operand 1 "register_operand" "k")))) "c86-4g-m7-direct,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_mskmov_k_reg" 3 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "mskmov") (and (match_operand 0 "register_operand" "k") (match_operand 1 "register_operand" "r")))) "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-fpu_1_3") (define_insn_reservation "c86_4g_m7_avx512_mskmov_k_m" 9 - (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") (and (eq_attr "type" "mskmov") (and (match_operand 0 "register_operand" "k") (match_operand 1 "memory_operand")))) diff --git a/gcc/config/i386/driver-i386.cc b/gcc/config/i386/driver-i386.cc index cd6a25e87ced..c7fb27769c75 100644 --- a/gcc/config/i386/driver-i386.cc +++ b/gcc/config/i386/driver-i386.cc @@ -508,8 +508,10 @@ const char *host_detect_local_cpu (int argc, const char **argv) processor = PROCESSOR_C86_4G_M4; else if (model == 6) processor = PROCESSOR_C86_4G_M6; - else if (model >= 7) + else if (model == 7) processor = PROCESSOR_C86_4G_M7; + else if (model >= 8) + processor = PROCESSOR_C86_4G_M8; } else if (vendor == VENDOR_CENTAUR) { @@ -869,6 +871,9 @@ const char *host_detect_local_cpu (int argc, const char **argv) case PROCESSOR_C86_4G_M7: cpu = "c86-4g-m7"; break; + case PROCESSOR_C86_4G_M8: + cpu = "c86-4g-m8"; + break; default: /* Use something reasonable. */ diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc index bf686c359e5c..a2749ae6b142 100644 --- a/gcc/config/i386/i386-c.cc +++ b/gcc/config/i386/i386-c.cc @@ -315,6 +315,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__c86_4g_m7"); def_or_undef (parse_in, "__c86_4g_m7__"); break; + case PROCESSOR_C86_4G_M8: + def_or_undef (parse_in, "__c86_4g_m8"); + def_or_undef (parse_in, "__c86_4g_m8__"); + break; /* use PROCESSOR_max to not set/unset the arch macro. */ case PROCESSOR_max: break; @@ -532,6 +536,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, case PROCESSOR_C86_4G_M7: def_or_undef (parse_in, "__tune_c86_4g_m7__"); break; + case PROCESSOR_C86_4G_M8: + def_or_undef (parse_in, "__tune_c86_4g_m8__"); + break; case PROCESSOR_INTEL: case PROCESSOR_GENERIC: break; diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index 7ffe9cd2a38c..dc7f8bf003f2 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -188,7 +188,9 @@ along with GCC; see the file COPYING3. If not see #define m_C86_4G_M4 (HOST_WIDE_INT_1U<<PROCESSOR_C86_4G_M4) #define m_C86_4G_M6 (HOST_WIDE_INT_1U<<PROCESSOR_C86_4G_M6) #define m_C86_4G_M7 (HOST_WIDE_INT_1U<<PROCESSOR_C86_4G_M7) -#define m_C86_4G (m_C86_4G_M4 | m_C86_4G_M6 | m_C86_4G_M7) +#define m_C86_4G_M8 (HOST_WIDE_INT_1U<<PROCESSOR_C86_4G_M8) +#define m_C86_4G (m_C86_4G_M4 | m_C86_4G_M6 | m_C86_4G_M7 \ + | m_C86_4G_M8) #define m_GENERIC (HOST_WIDE_INT_1U<<PROCESSOR_GENERIC) @@ -821,7 +823,8 @@ static const struct processor_costs *processor_cost_table[] = &znver5_cost, /* PROCESSOR_ZNVER6. */ &c86_4g_m4_cost, /* PROCESSOR_C86_4G_M4. */ &c86_4g_m6_cost, /* PROCESSOR_C86_4G_M6. */ - &c86_4g_m7_cost /* PROCESSOR_C86_4G_M7. */ + &c86_4g_m7_cost, /* PROCESSOR_C86_4G_M7. */ + &c86_4g_m8_cost /* PROCESSOR_C86_4G_M8. */ }; /* Guarantee that the array is aligned with enum processor_type. */ diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index 1974f05a0344..2a500e9745ac 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -25832,7 +25832,8 @@ ix86_reassociation_width (unsigned int op, machine_mode mode) || ix86_tune == PROCESSOR_ZNVER3 || ix86_tune == PROCESSOR_ZNVER4 || ix86_tune == PROCESSOR_C86_4G_M4 || ix86_tune == PROCESSOR_C86_4G_M6 - || ix86_tune == PROCESSOR_C86_4G_M7) + || ix86_tune == PROCESSOR_C86_4G_M7 + || ix86_tune == PROCESSOR_C86_4G_M8) && INTEGRAL_MODE_P (mode) && op != PLUS && op != MINUS) return 1; /* Znver5 can do 2 integer multiplications per cycle with latency diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index e4e6faab7931..85bbbe2fa374 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -2388,6 +2388,7 @@ enum processor_type PROCESSOR_C86_4G_M4, PROCESSOR_C86_4G_M6, PROCESSOR_C86_4G_M7, + PROCESSOR_C86_4G_M8, PROCESSOR_max }; @@ -2565,6 +2566,7 @@ constexpr wide_int_bitmask PTA_C86_4G_M7 = PTA_C86_4G_M4 | PTA_AVX512F | PTA_AVX512VNNI | PTA_AVX512BITALG | PTA_AVX512VPOPCNTDQ | PTA_AVX512VP2INTERSECT | PTA_VAES | PTA_AVXVNNI | PTA_VPCLMULQDQ | PTA_WBNOINVD | PTA_CLWB; +constexpr wide_int_bitmask PTA_C86_4G_M8 = PTA_C86_4G_M7; #ifndef GENERATOR_FILE diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 62bdff4dba8f..8407af948fc4 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -530,7 +530,7 @@ (define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,nehalem, atom,slm,glm,haswell,generic,lujiazui,yongfeng,amdfam10,bdver1, bdver2,bdver3,bdver4,btver2,znver1,znver2,znver3,znver4, - znver5,znver6,c86_4g_m4,c86_4g_m6,c86_4g_m7" + znver5,znver6,c86_4g_m4,c86_4g_m6,c86_4g_m7,c86_4g_m8" (const (symbol_ref "ix86_schedule"))) ;; A basic instruction type. Refinements due to arguments to be @@ -1429,7 +1429,7 @@ (include "lujiazui.md") (include "yongfeng.md") (include "c86-4g.md") -(include "c86-4g-m7.md") +(include "c86-4g-m7m8.md") ;; Operand and operator predicates and constraints diff --git a/gcc/config/i386/x86-tune-costs.h b/gcc/config/i386/x86-tune-costs.h index d2566bdbdcb7..fcf825674407 100644 --- a/gcc/config/i386/x86-tune-costs.h +++ b/gcc/config/i386/x86-tune-costs.h @@ -4720,3 +4720,5 @@ struct processor_costs c86_4g_m7_cost = { 2, /* Small unroll factor. */ COSTS_N_INSNS (2), /* Branch mispredict scale. */ }; + +struct processor_costs c86_4g_m8_cost = c86_4g_m7_cost; diff --git a/gcc/config/i386/x86-tune-sched.cc b/gcc/config/i386/x86-tune-sched.cc index 4fc955a12a5a..f4eba264c6c3 100644 --- a/gcc/config/i386/x86-tune-sched.cc +++ b/gcc/config/i386/x86-tune-sched.cc @@ -94,6 +94,7 @@ ix86_issue_rate (void) case PROCESSOR_C86_4G_M4: case PROCESSOR_C86_4G_M6: case PROCESSOR_C86_4G_M7: + case PROCESSOR_C86_4G_M8: return 4; case PROCESSOR_ICELAKE_CLIENT: @@ -446,6 +447,7 @@ ix86_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost, case PROCESSOR_C86_4G_M4: case PROCESSOR_C86_4G_M6: case PROCESSOR_C86_4G_M7: + case PROCESSOR_C86_4G_M8: /* Stack engine allows to execute push&pop instructions in parall. */ if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP) && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP)) diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def index 5f070e9c09f5..fecca3bb7777 100644 --- a/gcc/config/i386/x86-tune.def +++ b/gcc/config/i386/x86-tune.def @@ -545,7 +545,7 @@ DEF_TUNE (X86_TUNE_USE_GATHER_2PARTS, "use_gather_2parts", /* X86_TUNE_USE_SCATTER_2PARTS: Use scater instructions for vectors with 2 elements. */ DEF_TUNE (X86_TUNE_USE_SCATTER_2PARTS, "use_scatter_2parts", - ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7)) + ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7 | m_C86_4G_M8)) /* X86_TUNE_USE_GATHER_4PARTS: Use gather instructions for vectors with 4 @@ -558,7 +558,7 @@ DEF_TUNE (X86_TUNE_USE_GATHER_4PARTS, "use_gather_4parts", /* X86_TUNE_USE_SCATTER_4PARTS: Use scater instructions for vectors with 4 elements. */ DEF_TUNE (X86_TUNE_USE_SCATTER_4PARTS, "use_scatter_4parts", - ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7)) + ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7 | m_C86_4G_M8)) /* X86_TUNE_USE_GATHER: Use gather instructions for vectors with 8 or more elements. */ @@ -569,7 +569,7 @@ DEF_TUNE (X86_TUNE_USE_GATHER_8PARTS, "use_gather_8parts", /* X86_TUNE_USE_SCATTER: Use scater instructions for vectors with 8 or more elements. */ DEF_TUNE (X86_TUNE_USE_SCATTER_8PARTS, "use_scatter_8parts", - ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7)) + ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7 | m_C86_4G_M8)) /* X86_TUNE_AVOID_128FMA_CHAINS: Avoid creating loops with tight 128bit or smaller FMA chain. */ @@ -604,7 +604,8 @@ DEF_TUNE (X86_TUNE_SSE_MOVCC_USE_BLENDV, /* X86_TUNE_V4SI_REDUCTION_PREFER_SHUFD: Prefer pshuf to reduce V16QI, V8HI, V8HI, V4SI, V4FI, V2DI modes when lshr are costlier. */ DEF_TUNE (X86_TUNE_SSE_REDUCTION_PREFER_PSHUF, - "sse_reduction_prefer_pshuf", m_ZNVER4 | m_ZNVER5 | m_C86_4G_M7) + "sse_reduction_prefer_pshuf", m_ZNVER4 | m_ZNVER5 | m_C86_4G_M7 + | m_C86_4G_M8) /*****************************************************************************/ /* AVX instruction selection tuning (some of SSE flags affects AVX, too) */ @@ -640,7 +641,7 @@ DEF_TUNE (X86_TUNE_AVX256_AVOID_VEC_PERM, /* X86_TUNE_AVX256_SPLIT_REGS: if true, AVX512 ops are split into two AVX256 ops. */ DEF_TUNE (X86_TUNE_AVX512_SPLIT_REGS, "avx512_split_regs", m_ZNVER4 - | m_C86_4G_M7) + | m_C86_4G_M7 | m_C86_4G_M8) /* It's better to align MOVE_MAX with prefer_vector_width to reduce risk of STLF stalls(small store followed by big load.) */ @@ -653,7 +654,7 @@ DEF_TUNE (X86_TUNE_AVX256_MOVE_BY_PIECES, "avx256_move_by_pieces", /* X86_TUNE_AVX512_MOVE_BY_PIECES: Optimize move_by_pieces with 512-bit AVX instructions. */ DEF_TUNE (X86_TUNE_AVX512_MOVE_BY_PIECES, "avx512_move_by_pieces", - m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7) + m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7 | m_C86_4G_M8) /* X86_TUNE_AVX512_TWO_EPILOGUES: Use two vector epilogues for 512-bit vectorized loops. */ @@ -663,7 +664,7 @@ DEF_TUNE (X86_TUNE_AVX512_TWO_EPILOGUES, "avx512_two_epilogues", /* X86_TUNE_AVX512_MAKED_EPILOGUES: Use two masked vector epilogues when fit. */ DEF_TUNE (X86_TUNE_AVX512_MASKED_EPILOGUES, "avx512_masked_epilogues", - m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7) + m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7 | m_C86_4G_M8) /*****************************************************************************/ /*****************************************************************************/ diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 5f8aa3575e92..4e7cc15fa9b6 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -29101,6 +29101,9 @@ HYGON Family 18h model 6 shanghai CPU. @item c86-4g-m7 HYGON Family 18h model 7 chengdu CPU. + +@item c86-4g-m8 +HYGON Family 18h model 8 suzhou CPU. @end table Here is an example: diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index ac98c50ea9ad..2e2371b914be 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -35412,6 +35412,15 @@ CLFLUSHOPT, XSAVES, LZCNT, POPCNT, AVX512F, AVX512DQ, AVX512IFMA, AVX512CD, AVX512BW, AVX512VL, AVX512BF16, AVX512VBMI, AVX512VBMI2, GFNI, AVX512VNNI, VAES, AVX512BITALG, AVX512VPOPCNTDQ, AVX512VP2INTERSECT, AVXVNNI, VPCLMULQDQ, WBNOINVD instruction set support. + +@item c86-4g-m8 +HYGON c86-4g-m8 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSE4A, CX16, ABM, SSSE3, +SSE4.1, SSE4.2, AES, PCLMUL, AVX, AVX2, BMI, BMI2, F16C, FMA, PRFCHW, FXSR, SHA, +XSAVE, XSAVEOPT, XSAVEC, FSGSBASE, RDRND, MOVBE, MWAITX, ADX, RDSEED, CLZERO, +CLFLUSHOPT, XSAVES, LZCNT, POPCNT, AVX512F, AVX512DQ, AVX512IFMA, AVX512CD, +AVX512BW, AVX512VL, AVX512BF16, AVX512VBMI, AVX512VBMI2, GFNI, AVX512VNNI, VAES, +AVX512BITALG, AVX512VPOPCNTDQ, AVX512VP2INTERSECT, AVXVNNI, VPCLMULQDQ, +WBNOINVD instruction set support. @end table @opindex mtune diff --git a/gcc/testsuite/g++.target/i386/mv33.C b/gcc/testsuite/g++.target/i386/mv33.C index 8591690d2ccf..12ca1754116c 100644 --- a/gcc/testsuite/g++.target/i386/mv33.C +++ b/gcc/testsuite/g++.target/i386/mv33.C @@ -25,6 +25,10 @@ int __attribute__ ((target("arch=c86-4g-m7"))) foo () { return 3; } +int __attribute__ ((target("arch=c86-4g-m8"))) foo () { + return 4; +} + int main () { int val = foo (); @@ -35,6 +39,8 @@ int main () assert (val == 2); else if (__builtin_cpu_is ("c86-4g-m7")) assert (val == 3); + else if (__builtin_cpu_is ("c86-4g-m8")) + assert (val == 4); else assert (val == 0); diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc index 43ccaa9d99f1..f41067560d00 100644 --- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc +++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc @@ -242,6 +242,7 @@ extern void test_arch_znver6 (void) __attribute__((__target__("arch= extern void test_arch_c86_4g_m4 (void) __attribute__((__target__("arch=c86-4g-m4"))); extern void test_arch_c86_4g_m6 (void) __attribute__((__target__("arch=c86-4g-m6"))); extern void test_arch_c86_4g_m7 (void) __attribute__((__target__("arch=c86-4g-m7"))); +extern void test_arch_c86_4g_m8 (void) __attribute__((__target__("arch=c86-4g-m8"))); extern void test_tune_nocona (void) __attribute__((__target__("tune=nocona"))); extern void test_tune_core2 (void) __attribute__((__target__("tune=core2"))); @@ -273,6 +274,7 @@ extern void test_tune_znver6 (void) __attribute__((__target__("tune= extern void test_tune_c86_4g_m4 (void) __attribute__((__target__("tune=c86-4g-m4"))); extern void test_tune_c86_4g_m6 (void) __attribute__((__target__("tune=c86-4g-m6"))); extern void test_tune_c86_4g_m7 (void) __attribute__((__target__("tune=c86-4g-m7"))); +extern void test_tune_c86_4g_m8 (void) __attribute__((__target__("tune=c86-4g-m8"))); extern void test_fpmath_sse (void) __attribute__((__target__("sse2,fpmath=sse"))); extern void test_fpmath_387 (void) __attribute__((__target__("sse2,fpmath=387")));
