https://gcc.gnu.org/g:e45e4854b81b9fe75ebf2c0af7f9004cb1ea87d0
commit r17-2294-ge45e4854b81b9fe75ebf2c0af7f9004cb1ea87d0 Author: Pan Li <[email protected]> Date: Wed Jul 8 13:57:04 2026 +0800 RISC-V: Add test cases for vzext.vf4 reg overlap Add test cases for vzext.vf4 register group overlap, please note it is not overlap as much as possible. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf8.c: New test. Signed-off-by: Pan Li <[email protected]> Diff: --- .../rvv/autovec/group_overlap/vzext_vf4-u16-m1.c | 17 ++++++++++++++++ .../rvv/autovec/group_overlap/vzext_vf4-u16-m2.c | 17 ++++++++++++++++ .../rvv/autovec/group_overlap/vzext_vf4-u16-mf2.c | 23 ++++++++++++++++++++++ .../rvv/autovec/group_overlap/vzext_vf4-u16-mf4.c | 23 ++++++++++++++++++++++ .../rvv/autovec/group_overlap/vzext_vf4-u8-m1.c | 17 ++++++++++++++++ .../rvv/autovec/group_overlap/vzext_vf4-u8-m2.c | 17 ++++++++++++++++ .../rvv/autovec/group_overlap/vzext_vf4-u8-mf2.c | 23 ++++++++++++++++++++++ .../rvv/autovec/group_overlap/vzext_vf4-u8-mf4.c | 23 ++++++++++++++++++++++ .../rvv/autovec/group_overlap/vzext_vf4-u8-mf8.c | 23 ++++++++++++++++++++++ 9 files changed, 183 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m1.c new file mode 100644 index 000000000000..cce2d1a94266 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e16m1, + vuint16m1_t, + vuint64m4_t, + __riscv_vle16_v_u16m1, + __riscv_vzext_vf4_u64m4, + __riscv_vse64_v_u64m4, + vzext_vf, + LOOP_UNARY_BODY_X8) + +/* { dg-final { scan-assembler-times {vzext\.vf4\s+v0,v3([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vzext\.vf4\s+v4,v7} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m2.c new file mode 100644 index 000000000000..845917e4eea6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e16m2, + vuint16m2_t, + vuint64m8_t, + __riscv_vle16_v_u16m2, + __riscv_vzext_vf4_u64m8, + __riscv_vse64_v_u64m8, + vzext_vf, + LOOP_UNARY_BODY_X4) + +/* { dg-final { scan-assembler-times {vzext\.vf4\s+v0,v6} 1 } } */ +/* { dg-final { scan-assembler-times {vzext\.vf4\s+v8,v14} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf2.c new file mode 100644 index 000000000000..c56b984c5c8b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf2.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e16m1, + vuint16mf2_t, + vuint64m2_t, + __riscv_vle16_v_u16mf2, + __riscv_vzext_vf4_u64m2, + __riscv_vse64_v_u64m2, + vzext_vf, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v0,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v4,v7} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v8,v11} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v12,v15} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v16,v19} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v20,v23} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v24,v27} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v28,v31} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf4.c new file mode 100644 index 000000000000..055839b8e947 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf4.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e16m1, + vuint16mf4_t, + vuint64m1_t, + __riscv_vle16_v_u16mf4, + __riscv_vzext_vf4_u64m1, + __riscv_vse64_v_u64m1, + vzext_vf, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v0,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v4,v7} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v8,v11} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v12,v15} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v16,v19} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v20,v23} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v24,v27} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v28,v31} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m1.c new file mode 100644 index 000000000000..525be7621a4d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e8m1, + vuint8m1_t, + vuint32m4_t, + __riscv_vle8_v_u8m1, + __riscv_vzext_vf4_u32m4, + __riscv_vse32_v_u32m4, + vzext_vf, + LOOP_UNARY_BODY_X8) + +/* { dg-final { scan-assembler-times {vzext\.vf4\s+v0,v3([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vzext\.vf4\s+v4,v7} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m2.c new file mode 100644 index 000000000000..159808de53a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e8m2, + vuint8m2_t, + vuint32m8_t, + __riscv_vle8_v_u8m2, + __riscv_vzext_vf4_u32m8, + __riscv_vse32_v_u32m8, + vzext_vf, + LOOP_UNARY_BODY_X4) + +/* { dg-final { scan-assembler-times {vzext\.vf4\s+v0,v6} 1 } } */ +/* { dg-final { scan-assembler-times {vzext\.vf4\s+v8,v14} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf2.c new file mode 100644 index 000000000000..9188968bb950 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf2.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e8m1, + vuint8mf2_t, + vuint32m2_t, + __riscv_vle8_v_u8mf2, + __riscv_vzext_vf4_u32m2, + __riscv_vse32_v_u32m2, + vzext_vf, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v0,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v4,v7} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v8,v11} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v12,v15} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v16,v19} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v20,v23} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v24,v27} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v28,v31} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf4.c new file mode 100644 index 000000000000..b5d233b5d6e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf4.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e8m1, + vuint8mf4_t, + vuint32m1_t, + __riscv_vle8_v_u8mf4, + __riscv_vzext_vf4_u32m1, + __riscv_vse32_v_u32m1, + vzext_vf, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v0,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v4,v7} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v8,v11} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v12,v15} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v16,v19} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v20,v23} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v24,v27} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v28,v31} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf8.c new file mode 100644 index 000000000000..a8aab4cfc0e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e8m1, + vuint8mf8_t, + vuint32mf2_t, + __riscv_vle8_v_u8mf8, + __riscv_vzext_vf4_u32mf2, + __riscv_vse32_v_u32mf2, + vzext_vf, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v0,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v4,v7} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v8,v11} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v12,v15} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v16,v19} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v20,v23} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v24,v27} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v28,v31} } } */
