https://gcc.gnu.org/g:1f54efacc155831aebc13f17f036adec2b56e2ec
commit r17-4381-g1f54efacc155831aebc13f17f036adec2b56e2ec Author: Claudiu Zissulescu <[email protected]> Date: Thu Sep 17 10:54:43 2026 +0300 arc: Remove the unused "cond" attribute The "cond" attribute describes how each instruction uses or sets the condition codes, but nothing reads it anymore: no code in the compiler calls get_attr_cond, and genattr does not even emit a declaration for it, so the attribute table genattrtab computes for it is dead code. Remove the attribute definition, all the (set_attr "cond" ...) specifications, and the comments which describe the attribute. No functional change. gcc/ChangeLog: * config/arc/arc.md: Remove the "cond" attribute definition, all its uses and the comments describing it. * config/arc/fpu.md: Likewise. * config/arc/fpx.md: Likewise. * config/arc/simdext.md: Likewise. Signed-off-by: Claudiu Zissulescu <[email protected]> Diff: --- gcc/config/arc/arc.md | 341 +++++++++-------------------------------- gcc/config/arc/fpu.md | 18 --- gcc/config/arc/fpx.md | 28 +--- gcc/config/arc/simdext.md | 381 ++++++++++++++++------------------------------ 4 files changed, 206 insertions(+), 562 deletions(-) diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 54b65fefe6ac..e0f132118997 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -335,88 +335,6 @@ (const_string "yes"))) (define_attr "predicable" "no,yes" (const_string "no")) -;; if 'predicable' were not so brain-dead, we would specify: -;; (cond [(eq_attr "cond" "!canuse") (const_string "no") -;; (eq_attr "iscompact" "maybe") (const_string "no")] -;; (const_string "yes")) -;; and then for everything but calls, we could just set the cond attribute. - -;; Condition codes: this one is used by final_prescan_insn to speed up -;; conditionalizing instructions. It saves having to scan the rtl to see if -;; it uses or alters the condition codes. - -;; USE: This insn uses the condition codes (eg: a conditional branch). -;; CANUSE: This insn can use the condition codes (for conditional execution). -;; SET: All condition codes are set by this insn. -;; SET_ZN: the Z and N flags are set by this insn. -;; SET_ZNC: the Z, N, and C flags are set by this insn. -;; CLOB: The condition codes are set to unknown values by this insn. -;; NOCOND: This insn can't use and doesn't affect the condition codes. - -(define_attr "cond" "use,canuse,canuse_limm,canuse_limm_add,set,set_zn,clob,nocond" - (cond - [(and (eq_attr "predicable" "yes") - (eq_attr "is_sfunc" "no") - (eq_attr "delay_slot_filled" "no")) - (const_string "canuse") - - (eq_attr "type" "call") - (cond [(eq_attr "delay_slot_filled" "yes") (const_string "nocond") - (match_test "!flag_pic") (const_string "canuse_limm")] - (const_string "nocond")) - - (eq_attr "iscompact" "maybe,false") - (cond [ (and (eq_attr "type" "move") - (match_operand 1 "immediate_operand" "")) - (if_then_else - (ior (match_operand 1 "u6_immediate_operand" "") - (match_operand 1 "long_immediate_operand" "")) - (const_string "canuse") - (const_string "canuse_limm")) - - (eq_attr "type" "binary") - (cond [(ne (symbol_ref "REGNO (operands[0])") - (symbol_ref "REGNO (operands[1])")) - (const_string "nocond") - (match_operand 2 "register_operand" "") - (const_string "canuse") - (match_operand 2 "u6_immediate_operand" "") - (const_string "canuse") - (match_operand 2 "long_immediate_operand" "") - (const_string "canuse") - (match_operand 2 "const_int_operand" "") - (const_string "canuse_limm")] - (const_string "nocond")) - - (eq_attr "type" "compare") - (const_string "set") - - (eq_attr "type" "cmove,branch") - (const_string "use") - - (eq_attr "is_sfunc" "yes") - (cond [(match_test "(TARGET_MEDIUM_CALLS - && !TARGET_LONG_CALLS_SET - && flag_pic)") - (const_string "canuse_limm_add") - (match_test "(TARGET_MEDIUM_CALLS - && !TARGET_LONG_CALLS_SET)") - (const_string "canuse_limm")] - (const_string "canuse")) - - ] - - (const_string "nocond"))] - - (cond [(eq_attr "type" "compare") - (const_string "set") - - (eq_attr "type" "cmove,branch") - (const_string "use") - - ] - - (const_string "nocond")))) /* ??? Having all these patterns gives ifcvt more freedom to generate inefficient code. It seem to operate on the premise that @@ -502,8 +420,7 @@ ;; (define_asm_attributes [(set_attr "length" "8") - (set_attr "type" "multi") - (set_attr "cond" "clob") ]) + (set_attr "type" "multi") ]) ;; Delay slots. ;; The first two cond clauses and the default are necessary for correctness; @@ -851,8 +768,7 @@ archs4x, archs4xd" (const_int 0)))] "" "<SEZ_prefix><SQH_postfix>.f\\t0,%1" - [(set_attr "type" "compare") - (set_attr "cond" "set_zn")]) + [(set_attr "type" "compare") ]) (define_insn "*<SEZ_prefix>xt<SQH_postfix>_cmp0" [(set (match_operand 0 "cc_set_register" "") @@ -862,8 +778,7 @@ archs4x, archs4xd" (SEZ:SI (match_dup 1)))] "" "<SEZ_prefix><SQH_postfix>.f\\t%2,%1" - [(set_attr "type" "compare") - (set_attr "cond" "set_zn")]) + [(set_attr "type" "compare") ]) (define_insn "*xbfu_cmp0_noout" [(set (match_operand 0 "cc_set_register" "") @@ -882,8 +797,7 @@ archs4x, archs4xd" [(set_attr "type" "shift") (set_attr "iscompact" "false") (set_attr "length" "4,8") - (set_attr "predicable" "no") - (set_attr "cond" "set_zn")]) + (set_attr "predicable" "no") ]) (define_insn "*xbfu_cmp0" [(set (match_operand 4 "cc_set_register" "") @@ -904,8 +818,7 @@ archs4x, archs4xd" [(set_attr "type" "shift") (set_attr "iscompact" "false") (set_attr "length" "4,8,8") - (set_attr "predicable" "yes,no,yes") - (set_attr "cond" "set_zn")]) + (set_attr "predicable" "yes,no,yes") ]) ; splitting to 'tst' allows short insns and combination into brcc. (define_insn_and_split "*movsi_set_cc_insn" @@ -922,7 +835,6 @@ archs4x, archs4xd" "" [(set_attr "type" "compare") (set_attr "predicable" "yes,no,yes") - (set_attr "cond" "set_zn") (set_attr "length" "4,4,8")]) (define_insn "unary_comparison" @@ -933,8 +845,7 @@ archs4x, archs4xd" (const_int 0)]))] "" "%O2.f 0,%1" - [(set_attr "type" "compare") - (set_attr "cond" "set_zn")]) + [(set_attr "type" "compare") ]) ; this pattern is needed by combiner for cases like if (c=(~b)) { ... } @@ -949,7 +860,6 @@ archs4x, archs4xd" "" "%O3.f\\t%0,%1" [(set_attr "type" "compare") - (set_attr "cond" "set_zn") (set_attr "length" "4")]) ; reload is too stingy with reloads for Rrq/Cbf/Rrq when it sees @@ -1006,8 +916,7 @@ archs4x, archs4xd" [(set_attr "iscompact" "maybe,maybe,false,false,false,false,false,false") (set_attr "type" "compare,compare,compare,compare,compare,compare,binary,compare") (set_attr "length" "*,*,4,4,4,4,4,8") - (set_attr "predicable" "no,yes,no,yes,no,no,no,yes") - (set_attr "cond" "set_zn")]) + (set_attr "predicable" "no,yes,no,yes,no,no,no,yes") ]) ; ??? Sometimes, if an AND with a constant can be expressed as a zero_extract, ; combine will do that and not try the AND. @@ -1031,7 +940,6 @@ archs4x, archs4xd" && INTVAL (operands[3]) + INTVAL (operands[2]) == 32))" "tst\\t%1,((1<<%2)-1)<<%3" [(set_attr "type" "compare") - (set_attr "cond" "set_zn") (set_attr "length" "4")]) ; Likewise for asr.f. @@ -1047,7 +955,6 @@ archs4x, archs4xd" && INTVAL (operands[3]) + INTVAL (operands[2]) == 32" "asr.f 0,%1,%3" [(set_attr "type" "shift") - (set_attr "cond" "set_zn") (set_attr "length" "4")]) (define_insn "*tst_bitfield" @@ -1068,7 +975,6 @@ archs4x, archs4xd" and.f\\t0,%1,((1<<%2)-1)<<%3" [(set_attr "iscompact" "maybe,false,false,false,false") (set_attr "type" "compare,compare,compare,shift,compare") - (set_attr "cond" "set_zn") (set_attr "length" "*,4,4,4,8")]) (define_expand "<su_optab>mulvsi4" @@ -1138,7 +1044,6 @@ archs4x, archs4xd" "" "%O3.f\\t0,%1,%2" [(set_attr "type" "compare") - (set_attr "cond" "set_zn") (set_attr "length" "4,8")]) (define_insn "*commutative_binary_cmp0" @@ -1153,7 +1058,6 @@ archs4x, archs4xd" "" "%O4.f\\t%0,%1,%2" [(set_attr "type" "compare") - (set_attr "cond" "set_zn") (set_attr "predicable" "yes,yes,no,no") (set_attr "length" "4,4,4,8")]) @@ -1166,8 +1070,7 @@ archs4x, archs4xd" (match_operand:SI 1 "register_operand" "r")))] "" "add.f\\t0,%0,%1" - [(set_attr "cond" "set") - (set_attr "type" "compare") + [(set_attr "type" "compare") (set_attr "length" "4")]) (define_insn "addsi_compare_2" @@ -1177,8 +1080,7 @@ archs4x, archs4xd" (match_dup 0)))] "" "add.f\\t0,%0,%1" - [(set_attr "cond" "set") - (set_attr "type" "compare") + [(set_attr "type" "compare") (set_attr "length" "4,8")]) (define_insn "*addsi_compare_3" @@ -1188,8 +1090,7 @@ archs4x, archs4xd" (match_dup 1)))] "" "add.f\\t0,%0,%1" - [(set_attr "cond" "set") - (set_attr "type" "compare") + [(set_attr "type" "compare") (set_attr "length" "4")]) ; this pattern is needed by combiner for cases like if (c=a+b) { ... } @@ -1207,7 +1108,6 @@ archs4x, archs4xd" "" "%O4.f\\t%0,%1,%2 ; non-mult commutative" [(set_attr "type" "compare,compare,compare") - (set_attr "cond" "set_zn,set_zn,set_zn") (set_attr "length" "4,4,8")]) ; a MULT-specific version of this pattern to avoid touching the @@ -1225,7 +1125,6 @@ archs4x, archs4xd" "!TARGET_ARC600_FAMILY" "%O4.f\\t%0,%1,%2 ; mult commutative" [(set_attr "type" "compare,compare,compare") - (set_attr "cond" "set_zn,set_zn,set_zn") (set_attr "length" "4,4,8")]) (define_insn "*noncommutative_binary_cmp0" @@ -1240,7 +1139,6 @@ archs4x, archs4xd" "" "%O4%?.f\\t%0,%1,%2" [(set_attr "type" "compare") - (set_attr "cond" "set_zn") (set_attr "predicable" "yes,no,no,yes,no") (set_attr "length" "4,4,4,8,8")]) @@ -1254,7 +1152,6 @@ archs4x, archs4xd" "" "%O4.f\\t0,%1,%2" [(set_attr "type" "compare") - (set_attr "cond" "set_zn") (set_attr "length" "4,8")]) ;;rsub variants @@ -1270,7 +1167,6 @@ archs4x, archs4xd" "" "rsub.f\\t%0,%2,%1" [(set_attr "type" "compare") - (set_attr "cond" "set_zn") (set_attr "length" "4,8")]) (define_insn "*rsub_cmp0_noout" @@ -1283,7 +1179,6 @@ archs4x, archs4xd" "" "rsub.f\\t0,%2,%1" [(set_attr "type" "compare") - (set_attr "cond" "set_zn") (set_attr "length" "4,8")]) (define_expand "bic_f_zn" @@ -1309,7 +1204,6 @@ archs4x, archs4xd" "" "bic.f\\t%0,%1,%2" [(set_attr "type" "compare,compare,compare") - (set_attr "cond" "set_zn,set_zn,set_zn") (set_attr "length" "4,4,8")]) (define_insn "*bic_cmp0_noout" @@ -1322,7 +1216,6 @@ archs4x, archs4xd" || register_operand (operands[2], SImode)" "bic.f\\t0,%2,%1" [(set_attr "type" "unary") - (set_attr "cond" "set_zn") (set_attr "length" "4,8,8")]) (define_insn "*bic_cmp0" @@ -1337,7 +1230,6 @@ archs4x, archs4xd" || register_operand (operands[2], SImode)" "bic.f\\t%3,%2,%1" [(set_attr "type" "unary") - (set_attr "cond" "set_zn") (set_attr "length" "4,8,8")]) (define_expand "movdi" @@ -2094,7 +1986,6 @@ archs4x, archs4xd" (set_attr "iscompact" "false") (set_attr "type" "mul16_em") (set_attr "predicable" "yes,no,no,yes,no") - (set_attr "cond" "canuse,nocond,nocond,canuse_limm,nocond") ]) (define_insn "mulhisi3_reg" @@ -2107,7 +1998,6 @@ archs4x, archs4xd" (set_attr "iscompact" "maybe,false,false") (set_attr "type" "mul16_em") (set_attr "predicable" "yes,yes,no") - (set_attr "cond" "canuse,canuse,nocond") ]) (define_expand "umulhisi3" @@ -2134,7 +2024,6 @@ archs4x, archs4xd" (set_attr "iscompact" "false") (set_attr "type" "mul16_em") (set_attr "predicable" "yes,no,no,yes,no") - (set_attr "cond" "canuse,nocond,nocond,canuse_limm,nocond") ]) (define_insn "umulhisi3_reg" @@ -2147,7 +2036,6 @@ archs4x, archs4xd" (set_attr "iscompact" "maybe,false,false") (set_attr "type" "mul16_em") (set_attr "predicable" "yes,yes,no") - (set_attr "cond" "canuse,canuse,nocond") ]) ;; ARC700/ARC600/V2 multiply @@ -2216,8 +2104,7 @@ archs4x, archs4xd" "mululw\\t0,%0,%1" [(set_attr "length" "4,4,8") (set_attr "type" "mulmac_600") - (set_attr "predicable" "no") - (set_attr "cond" "nocond")]) + (set_attr "predicable" "no") ]) (define_insn "mac_600" [(set (match_operand:SI 2 "acc2_operand" "") @@ -2234,8 +2121,7 @@ archs4x, archs4xd" "machlw%?\\t0,%0,%1" [(set_attr "length" "4,4,8") (set_attr "type" "mulmac_600, mulmac_600, mulmac_600") - (set_attr "predicable" "no, no, yes") - (set_attr "cond" "nocond, canuse_limm, canuse")]) + (set_attr "predicable" "no, no, yes") ]) ; The gcc-internal representation may differ from the hardware ; register number in order to allow the generic code to correctly @@ -2269,8 +2155,7 @@ archs4x, archs4xd" [(set_attr "length" "*,4,4,8") (set_attr "iscompact" "maybe,false,false,false") (set_attr "type" "multi,multi,multi,multi") - (set_attr "predicable" "yes,yes,no,yes") - (set_attr "cond" "canuse,canuse,canuse_limm,canuse")]) + (set_attr "predicable" "yes,yes,no,yes") ]) (define_insn_and_split "mulsidi_600" [(set (match_operand:DI 0 "register_operand" "=r,r, r") @@ -2304,8 +2189,7 @@ archs4x, archs4xd" [(set_attr "length" "*,4,4,8") (set_attr "iscompact" "maybe,false,false,false") (set_attr "type" "multi,multi,multi,multi") - (set_attr "predicable" "yes,yes,no,yes") - (set_attr "cond" "canuse,canuse,canuse_limm,canuse")]) + (set_attr "predicable" "yes,yes,no,yes") ]) (define_insn_and_split "umulsidi_600" [(set (match_operand:DI 0 "register_operand" "=r,r, r") @@ -2339,8 +2223,7 @@ archs4x, archs4xd" [(set_attr "length" "4,4,8") (set_attr "iscompact" "false") (set_attr "type" "umulti") - (set_attr "predicable" "yes,no,yes") - (set_attr "cond" "canuse,canuse_limm,canuse")]) + (set_attr "predicable" "yes,no,yes") ]) ; ARC700 mpy* instructions: This is a multi-cycle extension, and thus 'w' ; may not be used as destination constraint. @@ -2358,8 +2241,7 @@ archs4x, archs4xd" "mpyu%?\\t%0,%1,%2" [(set_attr "length" "4,4,4,8,8") (set_attr "type" "umulti") - (set_attr "predicable" "yes,no,no,yes,no") - (set_attr "cond" "canuse,nocond,canuse_limm,canuse,nocond")]) + (set_attr "predicable" "yes,no,no,yes,no") ]) ; ARCv2 has no penalties between mpy and mpyu. So, we use mpy because of its ; short variant. LP_COUNT constraints are still valid. @@ -2379,8 +2261,7 @@ archs4x, archs4xd" [(set_attr "length" "*,*,4,4,4,8,8") (set_attr "iscompact" "maybe,maybe,false,false,false,false,false") (set_attr "type" "umulti") - (set_attr "predicable" "no,no,yes,no,no,yes,no") - (set_attr "cond" "nocond,nocond,canuse,nocond,canuse_limm,canuse,nocond")]) + (set_attr "predicable" "no,no,yes,no,no,yes,no") ]) (define_expand "mulsidi3" [(set (match_operand:DI 0 "register_operand" "") @@ -2462,8 +2343,7 @@ archs4x, archs4xd" "mullw%?\\t0,%0,%1" [(set_attr "length" "4,4,8") (set_attr "type" "mulmac_600") - (set_attr "predicable" "no,no,yes") - (set_attr "cond" "nocond, canuse_limm, canuse")]) + (set_attr "predicable" "no,no,yes") ]) ;; ??? check if this is canonical rtl @@ -2490,8 +2370,7 @@ archs4x, archs4xd" "machlw%?\\t%0,%1,%2" [(set_attr "length" "4,4,8") (set_attr "type" "mulmac_600") - (set_attr "predicable" "no,no,yes") - (set_attr "cond" "nocond, canuse_limm, canuse")]) + (set_attr "predicable" "no,no,yes") ]) ;; DI <- DI(signed SI) * DI(signed SI) @@ -2527,8 +2406,7 @@ archs4x, archs4xd" "mpy%+%?\\t%0,%1,%2" [(set_attr "length" "4,4,8,8") (set_attr "type" "multi") - (set_attr "predicable" "yes,no,yes,no") - (set_attr "cond" "canuse,nocond,canuse,nocond")]) + (set_attr "predicable" "yes,no,yes,no") ]) ; Note that mpyhu has the same latency as mpy / mpyh, ; thus we use the type multi. @@ -2544,8 +2422,7 @@ archs4x, archs4xd" "mpy%+u%?\\t%0,%1,%2" [(set_attr "length" "4,4,8,8") (set_attr "type" "multi") - (set_attr "predicable" "yes,no,yes,no") - (set_attr "cond" "canuse,nocond,canuse,nocond")]) + (set_attr "predicable" "yes,no,yes,no") ]) ;; (zero_extend:DI (const_int)) leads to internal errors in combine, so we ;; need a separate pattern for immediates @@ -2562,8 +2439,7 @@ archs4x, archs4xd" "mpy%+u%?\\t%0,%1,%2" [(set_attr "length" "4,4,4,8,8") (set_attr "type" "multi") - (set_attr "predicable" "yes,no,no,yes,no") - (set_attr "cond" "canuse,nocond,canuse_limm,canuse,nocond")]) + (set_attr "predicable" "yes,no,no,yes,no") ]) (define_expand "umulsi3_highpart" [(set (match_operand:SI 0 "general_operand" "") @@ -2677,8 +2553,7 @@ archs4x, archs4xd" "mululw\\t0,%0,%1" [(set_attr "length" "4,4,8") (set_attr "type" "mulmac_600") - (set_attr "predicable" "no") - (set_attr "cond" "nocond")]) + (set_attr "predicable" "no") ]) (define_insn "umac64_600" @@ -2704,8 +2579,7 @@ archs4x, archs4xd" "machulw%?\\t%0,%1,%2" [(set_attr "length" "4,4,8") (set_attr "type" "mulmac_600") - (set_attr "predicable" "no,no,yes") - (set_attr "cond" "nocond, canuse_limm, canuse")]) + (set_attr "predicable" "no,no,yes") ]) ;; DI <- DI(unsigned SI) * DI(unsigned SI) (define_insn_and_split "umulsidi3_700" @@ -2804,8 +2678,7 @@ archs4x, archs4xd" (sign_extend:DI (match_dup 2)))))] "" "add.f\\t%0,%1,%2" - [(set_attr "cond" "set") - (set_attr "type" "compare") + [(set_attr "type" "compare") (set_attr "length" "4,4,4,8")]) (define_expand "addvsi4" @@ -2828,8 +2701,7 @@ archs4x, archs4xd" (match_dup 1)))] "" "add.f\\t%0,%1,%2" - [(set_attr "cond" "set") - (set_attr "type" "compare") + [(set_attr "type" "compare") (set_attr "length" "4,4,4,8")]) (define_expand "uaddvsi4" @@ -2860,8 +2732,7 @@ archs4x, archs4xd" add.f\\t%0,%2,%1 add.f\\t%0,%2,%1 add.f\\t%0,%1,%2" - [(set_attr "cond" "set") - (set_attr "type" "compare") + [(set_attr "type" "compare") (set_attr "length" "4,4,4,4,8,8")]) (define_insn "*add_f_2" @@ -2874,8 +2745,7 @@ archs4x, archs4xd" (plus:SI (match_dup 1) (match_dup 2)))] "" "add.f\\t%0,%1,%2" - [(set_attr "cond" "set") - (set_attr "type" "compare") + [(set_attr "type" "compare") (set_attr "length" "4,4,8")]) (define_insn "adc" @@ -2894,8 +2764,7 @@ archs4x, archs4xd" adc\\t%0,%1,%2 adc\\t%0,%1,%2 adc\\t%0,%1,%2" - [(set_attr "cond" "use") - (set_attr "type" "cc_arith") + [(set_attr "type" "cc_arith") (set_attr "length" "4,4,4,4,8,8")]) (define_insn "adc_f" @@ -2918,8 +2787,7 @@ archs4x, archs4xd" (match_dup 2)))] "" "adc.f\\t%0,%1,%2" - [(set_attr "cond" "set") - (set_attr "predicable" "no") + [(set_attr "predicable" "no") (set_attr "type" "cc_arith") (set_attr "length" "4")]) @@ -2958,7 +2826,6 @@ archs4x, archs4xd" ; (match_operand:SI 1 "register_operand" "c")))] ; "" ; "adc\\t%0,%1,0" -; [(set_attr "cond" "use") ; (set_attr "type" "cc_arith") ; (set_attr "length" "4")]) ; @@ -3019,7 +2886,6 @@ archs4x, archs4xd" [(set_attr "iscompact" "maybe,maybe,false,false,false,false,false,false,false, false") (set_attr "length" "*,*,4,4,4,4,4,8,8,8") (set_attr "predicable" "yes,no,yes,yes,no,no,no,yes,no,no") - (set_attr "cond" "canuse,nocond,canuse,canuse,nocond,nocond,canuse_limm,canuse,nocond,nocond") (set_attr "cpu_facility" "*,cd,*,*,*,*,*,*,*,*") ]) @@ -3034,8 +2900,7 @@ archs4x, archs4xd" (sign_extend:DI (match_dup 2)))))] "" "sub.f\\t%0,%1,%2" - [(set_attr "cond" "set") - (set_attr "type" "compare") + [(set_attr "type" "compare") (set_attr "length" "4,4,4,8")]) (define_expand "subvsi4" @@ -3057,8 +2922,7 @@ archs4x, archs4xd" (match_dup 2)))] "" "sub.f\\t%0,%1,%2" - [(set_attr "cond" "set") - (set_attr "type" "compare") + [(set_attr "type" "compare") (set_attr "length" "4,4,4,8")]) (define_expand "usubvsi4" @@ -3112,8 +2976,7 @@ archs4x, archs4xd" (const_int 0))))] "" "sbc\\t%0,%1,0" - [(set_attr "cond" "use") - (set_attr "type" "cc_arith") + [(set_attr "type" "cc_arith") (set_attr "length" "4")]) (define_insn "sbc" @@ -3132,8 +2995,7 @@ archs4x, archs4xd" sbc\\t%0,%1,%2 sbc\\t%0,%1,%2 sbc\\t%0,%1,%2" - [(set_attr "cond" "use") - (set_attr "type" "cc_arith") + [(set_attr "type" "cc_arith") (set_attr "length" "4,4,4,4,8,8")]) (define_insn "sub_f" @@ -3193,7 +3055,6 @@ archs4x, archs4xd" [(set_attr "type" "shift") (set_attr "length" "*,4,8") (set_attr "predicable" "yes,no,no") - (set_attr "cond" "canuse,nocond,nocond") (set_attr "iscompact" "maybe,false,false")]) ;; N.B. sub[123] has the operands of the MINUS in the opposite order from @@ -3208,7 +3069,6 @@ archs4x, archs4xd" [(set_attr "type" "shift") (set_attr "length" "4,4,8") (set_attr "predicable" "yes,no,no") - (set_attr "cond" "canuse,nocond,nocond") (set_attr "iscompact" "false")]) (define_insn "*sub_n" @@ -3221,7 +3081,6 @@ archs4x, archs4xd" [(set_attr "type" "shift") (set_attr "length" "4,4,8") (set_attr "predicable" "yes,no,no") - (set_attr "cond" "canuse,nocond,nocond") (set_attr "iscompact" "false")]) ; ??? check if combine matches this. @@ -3233,8 +3092,7 @@ archs4x, archs4xd" "" "bset%?\\t%0,%2,%1" [(set_attr "length" "4,4,8") - (set_attr "predicable" "yes,no,no") - (set_attr "cond" "canuse,nocond,nocond")] + (set_attr "predicable" "yes,no,no") ] ) ; ??? check if combine matches this. @@ -3246,8 +3104,7 @@ archs4x, archs4xd" "" "bxor%?\\t%0,%2,%1" [(set_attr "length" "4,4,8") - (set_attr "predicable" "yes,no,no") - (set_attr "cond" "canuse,nocond,nocond")] + (set_attr "predicable" "yes,no,no") ] ) ; ??? check if combine matches this. @@ -3259,8 +3116,7 @@ archs4x, archs4xd" "" "bclr%?\\t%0,%2,%1" [(set_attr "length" "4,4,8") - (set_attr "predicable" "yes,no,no") - (set_attr "cond" "canuse,nocond,nocond")] + (set_attr "predicable" "yes,no,no") ] ) ; ??? FIXME: find combine patterns for bmsk. @@ -3279,8 +3135,7 @@ archs4x, archs4xd" bset\\t%0,%1,%2 ;;peep2, constr 2 bset\\t%0,%1,%2 ;;peep2, constr 3" [(set_attr "length" "4,4,8") - (set_attr "predicable" "yes,no,no") - (set_attr "cond" "canuse,nocond,nocond")] + (set_attr "predicable" "yes,no,no") ] ) ; see also xorsi3 for use with constant bit number. @@ -3295,8 +3150,7 @@ archs4x, archs4xd" bxor\\t%0,%1,%2 bxor\\t%0,%1,%2" [(set_attr "length" "4,4,8") - (set_attr "predicable" "yes,no,no") - (set_attr "cond" "canuse,nocond,nocond")] + (set_attr "predicable" "yes,no,no") ] ) ; see also andsi3 for use with constant bit number. @@ -3311,8 +3165,7 @@ archs4x, archs4xd" bclr\\t%0,%1,%2 bclr\\t%0,%1,%2" [(set_attr "length" "4,4,8") - (set_attr "predicable" "yes,no,no") - (set_attr "cond" "canuse,nocond,nocond")] + (set_attr "predicable" "yes,no,no") ] ) ; see also andsi3 for use with constant bit number. @@ -3329,8 +3182,7 @@ archs4x, archs4xd" bmsk\\t%0,%1,%2 bmsk\\t%0,%1,%2" [(set_attr "length" "4,4,8") - (set_attr "predicable" "yes,no,no") - (set_attr "cond" "canuse,nocond,nocond")] + (set_attr "predicable" "yes,no,no") ] ) ;;Instructions added for peephole2s end @@ -3409,8 +3261,7 @@ archs4x, archs4xd" [(set_attr "iscompact" "maybe,maybe,maybe,maybe,true,false,false,false,false,false,false,false,false,false,false,false,false,false,false,false") (set_attr "type" "binary,binary,binary,binary,binary,binary,binary,binary,binary,binary,binary,binary,binary,binary,binary,shift,binary,binary,binary,load") (set_attr "length" "*,*,*,*,*,4,4,4,4,4,4,4,4,4,4,4,4,8,8,*") - (set_attr "predicable" "no,no,no,no,no,yes,yes,yes,yes,yes,no,no,no,no,no,no,no,yes,no,no") - (set_attr "cond" "canuse,canuse,canuse,canuse,nocond,canuse,canuse,canuse,canuse,canuse,canuse_limm,nocond,nocond,nocond,nocond,nocond,canuse_limm,canuse,nocond,nocond")]) + (set_attr "predicable" "no,no,no,no,no,yes,yes,yes,yes,yes,no,no,no,no,no,no,no,yes,no,no") ]) ; combiner splitter, pattern found in ldtoa.c . ; and op3,op0,op1 / cmp op3,op2 -> add op3,op0,op4 / bmsk.f 0,op3,op1 @@ -3444,8 +3295,7 @@ archs4x, archs4xd" bic\\t%0,%2,%1 ;;constraint 6" [(set_attr "length" "*,4,4,8,4,8,8") (set_attr "iscompact" "maybe, false, false, false, false, false, false") - (set_attr "predicable" "no,yes,no,yes,no,no,no") - (set_attr "cond" "canuse,canuse,canuse_limm,canuse,nocond,nocond,nocond")]) + (set_attr "predicable" "no,yes,no,yes,no,no,no") ]) (define_insn_and_split "iorsi3" [(set (match_operand:SI 0 "dest_reg_operand" "=q,q, q, r,r, r,r, r, r,r, q, r, r") @@ -3478,8 +3328,7 @@ archs4x, archs4xd" " [(set_attr "iscompact" "maybe,maybe,maybe,false,false,false,false,false,false,false,false,false,false") (set_attr "length" "*,*,*,4,4,4,4,4,4,4,*,8,8") - (set_attr "predicable" "no,no,no,yes,yes,yes,no,no,no,no,no,yes,no") - (set_attr "cond" "canuse,canuse,canuse,canuse,canuse,canuse,canuse_limm,nocond,nocond,canuse_limm,nocond,canuse,nocond")]) + (set_attr "predicable" "no,no,no,yes,yes,yes,no,no,no,no,no,yes,no") ]) (define_insn "xorsi3" [(set (match_operand:SI 0 "dest_reg_operand" "=q,q, r,r, r,r, r, r,r, r, r") @@ -3502,8 +3351,7 @@ archs4x, archs4xd" [(set_attr "iscompact" "maybe,maybe,false,false,false,false,false,false,false,false,false") (set_attr "type" "binary") (set_attr "length" "*,*,4,4,4,4,4,4,4,8,8") - (set_attr "predicable" "no,no,yes,yes,yes,no,no,no,no,yes,no") - (set_attr "cond" "canuse,canuse,canuse,canuse,canuse,canuse_limm,nocond,nocond,canuse_limm,canuse,nocond")]) + (set_attr "predicable" "no,no,yes,yes,yes,no,no,no,no,yes,no") ]) (define_insn "negsi2" [(set (match_operand:SI 0 "dest_reg_operand" "=q,q,r,r") @@ -3539,7 +3387,6 @@ archs4x, archs4xd" operands[5] = operand_subword (operands[1], 1-swap, 0, DImode); } [(set_attr "type" "unary,unary") - (set_attr "cond" "nocond,nocond") (set_attr "length" "4,8")]) ;; Shift instructions. @@ -3580,8 +3427,7 @@ archs4x, archs4xd" "asl%?\\t%0,%1,%2" [(set_attr "type" "shift") (set_attr "iscompact" "maybe,maybe,maybe,false,false,false") - (set_attr "predicable" "no,no,no,yes,no,no") - (set_attr "cond" "canuse,nocond,canuse,canuse,nocond,nocond")]) + (set_attr "predicable" "no,no,no,yes,no,no") ]) (define_insn "*ashrsi3_insn" [(set (match_operand:SI 0 "dest_reg_operand" "=q,q, q, r, r, r") @@ -3593,8 +3439,7 @@ archs4x, archs4xd" "asr%?\\t%0,%1,%2" [(set_attr "type" "shift") (set_attr "iscompact" "maybe,maybe,maybe,false,false,false") - (set_attr "predicable" "no,no,no,yes,no,no") - (set_attr "cond" "canuse,nocond,canuse,canuse,nocond,nocond")]) + (set_attr "predicable" "no,no,no,yes,no,no") ]) (define_insn "*lshrsi3_insn" [(set (match_operand:SI 0 "dest_reg_operand" "=q, q, r, r, r") @@ -3611,8 +3456,7 @@ archs4x, archs4xd" lsr%?\\t%0,%1,%2" [(set_attr "type" "shift") (set_attr "iscompact" "maybe,maybe,false,false,false") - (set_attr "predicable" "no,no,yes,no,no") - (set_attr "cond" "nocond,canuse,canuse,nocond,nocond")]) + (set_attr "predicable" "no,no,yes,no,no") ]) (define_insn "<insn>si2_cnt16" [(set (match_operand:SI 0 "register_operand" "=r") @@ -3938,7 +3782,6 @@ archs4x, archs4xd" [(set_attr "type" "compare") (set_attr "iscompact" "true,true,true,false,false,true_limm,false") (set_attr "predicable" "no,no,no,no,yes,no,yes") - (set_attr "cond" "set") (set_attr "length" "*,*,*,4,4,*,8") (set_attr "cpu_facility" "av1,av2,*,*,*,*,*")]) @@ -3951,7 +3794,6 @@ archs4x, archs4xd" [(set_attr "type" "compare,compare") (set_attr "iscompact" "true,false") (set_attr "predicable" "no,yes") - (set_attr "cond" "set_zn") (set_attr "length" "*,4")]) ; combiner pattern observed for unwind-dw2-fde.c:linear_search_fdes. @@ -3966,7 +3808,6 @@ archs4x, archs4xd" "btst%?\\t%0,%1" [(set_attr "iscompact" "true,false") (set_attr "predicable" "no,yes") - (set_attr "cond" "set") (set_attr "type" "compare") (set_attr "length" "*,4")]) @@ -3980,7 +3821,6 @@ archs4x, archs4xd" bxor.f\\t0,%0,%z1" [(set_attr "type" "compare,compare") (set_attr "iscompact" "true,false") - (set_attr "cond" "set,set_zn") (set_attr "length" "*,4")]) (define_insn "*cmpsi_cc_c_insn" @@ -3991,7 +3831,6 @@ archs4x, archs4xd" "cmp%?\\t%0,%1" [(set_attr "type" "compare") (set_attr "iscompact" "true,true,true,false,true_limm,false") - (set_attr "cond" "set") (set_attr "length" "*,*,*,4,*,8") (set_attr "cpu_facility" "av1,av2,*,*,*,*")]) @@ -4115,8 +3954,7 @@ archs4x, archs4xd" arc_output_commutative_cond_exec (operands, true); return ""; } - [(set_attr "cond" "use") - (set_attr "type" "cmove") + [(set_attr "type" "cmove") (set_attr_alternative "length" [(const_int 4) (cond @@ -4137,8 +3975,7 @@ archs4x, archs4xd" sub.%d4\\t%0,%1,%2 rsub.%d4\\t%0,%2,%1 rsub.%d4\\t%0,%2,%1" - [(set_attr "cond" "use") - (set_attr "type" "cmove") + [(set_attr "type" "cmove") (set_attr "length" "4,4,8")]) (define_insn "*noncommutative_cond_exec" @@ -4151,8 +3988,7 @@ archs4x, archs4xd" (match_operand:SI 2 "nonmemory_operand" "cL,Cal")])))] "" "%O3.%d5\\t%0,%1,%2" - [(set_attr "cond" "use") - (set_attr "type" "cmove") + [(set_attr "type" "cmove") (set_attr "length" "4,8")]) ;; These control RTL generation for conditional jump insns @@ -4265,7 +4101,6 @@ archs4x, archs4xd" (set (attr "iscompact") (if_then_else (match_test "get_attr_length (insn) == 2") (const_string "true") (const_string "false"))) - (set_attr "cond" "canuse") (set (attr "length") (cond [ ; In arc_reorg we just guesstimate; might be more or less than 4. @@ -4295,8 +4130,7 @@ archs4x, archs4xd" j%!%*\\t[%0] j%!%*\\t[%0]" [(set_attr "type" "jump") - (set_attr "iscompact" "false,false,false,maybe,false") - (set_attr "cond" "canuse,canuse_limm,canuse,canuse,canuse")]) + (set_attr "iscompact" "false,false,false,maybe,false") ]) ;; Implement a switch statement. (define_expand "casesi" @@ -4423,8 +4257,7 @@ archs4x, archs4xd" "" "j%!%* [%0]" [(set_attr "type" "jump") - (set_attr "iscompact" "false,maybe,false") - (set_attr "cond" "canuse")]) + (set_attr "iscompact" "false,maybe,false") ]) (define_expand "call" ;; operands[1] is stack_size_rtx @@ -4532,7 +4365,6 @@ archs4x, archs4xd" "nop%?" [(set_attr "type" "misc") (set_attr "iscompact" "true") - (set_attr "cond" "canuse") (set_attr "length" "2")]) (define_insn "nopv" @@ -4848,8 +4680,7 @@ archs4x, archs4xd" flag%?\\t%0" [(set_attr "length" "4,4,8") (set_attr "type" "misc,misc,misc") - (set_attr "predicable" "yes,no,yes") - (set_attr "cond" "clob,clob,clob")]) + (set_attr "predicable" "yes,no,yes") ]) (define_insn "brk" [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "N")] @@ -4865,8 +4696,7 @@ archs4x, archs4xd" "!TARGET_ARC600_FAMILY" "rtie" [(set_attr "length" "4") - (set_attr "type" "rtie") - (set_attr "cond" "clob")]) + (set_attr "type" "rtie") ]) (define_insn "sync" [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "N")] @@ -5148,7 +4978,6 @@ archs4x, archs4xd" "" "j%!%*\\t[blink]" [(set_attr "type" "return") - (set_attr "cond" "canuse") (set_attr "iscompact" "maybe") (set_attr "length" "*")]) @@ -5159,8 +4988,7 @@ archs4x, archs4xd" "TARGET_ARC600_FAMILY" "j.f\\t[%0]" [(set_attr "length" "4") - (set_attr "type" "rtie") - (set_attr "cond" "clob")]) + (set_attr "type" "rtie") ]) (define_insn "p_return_i" [(set (pc) @@ -5170,7 +4998,6 @@ archs4x, archs4xd" "reload_completed" "j%d0%!%*\\t[blink]" [(set_attr "type" "return") - (set_attr "cond" "use") (set_attr "iscompact" "maybe" ) (set (attr "length") (cond [(not (match_operand 0 "equality_comparison_operator" "")) @@ -5217,8 +5044,7 @@ archs4x, archs4xd" default: fprintf (stderr, \"unexpected length %d\\n\", get_attr_length (insn)); fflush (stderr); gcc_unreachable (); } " - [(set_attr "cond" "clob, clob, clob") - (set (attr "type") + [(set (attr "type") (if_then_else (match_test "valid_brcc_with_delay_p (operands)") (const_string "brcc") @@ -5282,7 +5108,6 @@ archs4x, archs4xd" } } [(set_attr "type" "brcc") - (set_attr "cond" "clob") (set (attr "length") (cond [(and (ge (minus (match_dup 0) (pc)) (const_int -254)) (le (minus (match_dup 0) (pc)) @@ -5374,7 +5199,6 @@ archs4x, archs4xd" "sub.f%?\\tlp_count,lp_count,1" [(set_attr "iscompact" "false") (set_attr "type" "compare") - (set_attr "cond" "set_zn") (set_attr "length" "4") (set_attr "predicable" "yes")]) @@ -5557,7 +5381,6 @@ archs4x, archs4xd" ;; [(set_attr "type" "unary,unary,dpfp_addsub,dpfp_addsub") ;; (set_attr "iscompact" "false,false,false,false") ;; (set_attr "length" "4,4,8,12") -;; (set_attr "cond" "canuse,nocond,nocond,nocond")]) ;; and this suffers from always requiring a long immediate when using ;; the floating point hardware. ;; We then want the sub[sd]f patterns to be used, so that we can load the @@ -5639,7 +5462,6 @@ archs4x, archs4xd" (set_attr "iscompact" "false") (set_attr "type" "div_rem") (set_attr "predicable" "yes,no,no,yes,no,no,yes,no") - (set_attr "cond" "canuse,nocond,nocond,canuse,nocond,nocond,canuse,nocond") ]) (define_insn "udivsi3" @@ -5652,7 +5474,6 @@ archs4x, archs4xd" (set_attr "iscompact" "false") (set_attr "type" "div_rem") (set_attr "predicable" "yes,no,no,yes,no,no,yes,no") - (set_attr "cond" "canuse,nocond,nocond,canuse,nocond,nocond,canuse,nocond") ]) (define_insn "modsi3" @@ -5665,7 +5486,6 @@ archs4x, archs4xd" (set_attr "iscompact" "false") (set_attr "type" "div_rem") (set_attr "predicable" "yes,no,no,yes,no,no,yes,no") - (set_attr "cond" "canuse,nocond,nocond,canuse,nocond,nocond,canuse,nocond") ]) (define_insn "umodsi3" @@ -5678,7 +5498,6 @@ archs4x, archs4xd" (set_attr "iscompact" "false") (set_attr "type" "div_rem") (set_attr "predicable" "yes,no,no,yes,no,no,yes,no") - (set_attr "cond" "canuse,nocond,nocond,canuse,nocond,nocond,canuse,nocond") ]) ;; SETcc instructions @@ -5694,7 +5513,6 @@ archs4x, archs4xd" (set_attr "iscompact" "false") (set_attr "type" "compare") (set_attr "predicable" "yes,no,yes,no,no,yes,no") - (set_attr "cond" "canuse,nocond,canuse,nocond,nocond,canuse,nocond") ]) (define_insn "arcsetltu" @@ -5707,7 +5525,6 @@ archs4x, archs4xd" (set_attr "iscompact" "false") (set_attr "type" "compare") (set_attr "predicable" "yes,no,yes,no,no,yes,no") - (set_attr "cond" "canuse,nocond,canuse,nocond,nocond,canuse,nocond") ]) (define_insn "arcsetgeu" @@ -5720,7 +5537,6 @@ archs4x, archs4xd" (set_attr "iscompact" "false") (set_attr "type" "compare") (set_attr "predicable" "yes,no,yes,no,no,yes,no") - (set_attr "cond" "canuse,nocond,canuse,nocond,nocond,canuse,nocond") ]) ;; Special cases of SETCC @@ -5743,8 +5559,7 @@ archs4x, archs4xd" [(set_attr "length" "4,4,4,8") (set_attr "iscompact" "false") (set_attr "type" "compare") - (set_attr "predicable" "yes,no,no,no") - (set_attr "cond" "canuse,nocond,nocond,nocond")] + (set_attr "predicable" "yes,no,no,no") ] ) (define_insn_and_split "arcsetls" @@ -5766,8 +5581,7 @@ archs4x, archs4xd" [(set_attr "length" "4,4,4,8") (set_attr "iscompact" "false") (set_attr "type" "compare") - (set_attr "predicable" "yes,no,no,no") - (set_attr "cond" "canuse,nocond,nocond,nocond")] + (set_attr "predicable" "yes,no,no,no") ] ) ; Any mode that needs to be solved by secondary reload @@ -5807,8 +5621,7 @@ archs4x, archs4xd" [(set_attr "type" "shift") (set_attr "iscompact" "false") (set_attr "length" "4,4,8,8") - (set_attr "predicable" "yes,no,no,yes") - (set_attr "cond" "canuse,nocond,nocond,canuse_limm")]) + (set_attr "predicable" "yes,no,no,yes") ]) (define_insn "kflag" [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "rL,I,Cal")] @@ -5820,8 +5633,7 @@ archs4x, archs4xd" kflag%?\\t%0" [(set_attr "length" "4,4,8") (set_attr "type" "misc,misc,misc") - (set_attr "predicable" "yes,no,yes") - (set_attr "cond" "clob,clob,clob")]) + (set_attr "predicable" "yes,no,yes") ]) (define_insn "clri" [(set (match_operand:SI 0 "dest_reg_operand" "=r") @@ -6474,8 +6286,7 @@ archs4x, archs4xd" "dmach\\t%0,%1,%2" [(set_attr "length" "4") (set_attr "type" "multi") - (set_attr "predicable" "no") - (set_attr "cond" "nocond")]) + (set_attr "predicable" "no") ]) ; The same for the unsigned variant, but using VMAC2HU instruction. (define_expand "umaddhisi4" @@ -6503,8 +6314,7 @@ archs4x, archs4xd" "dmachu\\t%0,%1,%2" [(set_attr "length" "4") (set_attr "type" "multi") - (set_attr "predicable" "no") - (set_attr "cond" "nocond")]) + (set_attr "predicable" "no") ]) (define_expand "maddsidi4" [(match_operand:DI 0 "register_operand" "") @@ -6562,8 +6372,7 @@ archs4x, archs4xd" "macd\\t%0,%1,%2" [(set_attr "length" "4,4,8") (set_attr "type" "multi") - (set_attr "predicable" "yes,no,no") - (set_attr "cond" "canuse,nocond,nocond")]) + (set_attr "predicable" "yes,no,no") ]) (define_insn "mac" [(set (reg:DI ARCV2_ACC) @@ -6575,8 +6384,7 @@ archs4x, archs4xd" "mac 0,%0,%1" [(set_attr "length" "4,8") (set_attr "type" "multi") - (set_attr "predicable" "no") - (set_attr "cond" "nocond")]) + (set_attr "predicable" "no") ]) (define_peephole2 [(set (reg:DI ARCV2_ACC) @@ -6605,8 +6413,7 @@ archs4x, archs4xd" "mac\\t%0,%1,%2" [(set_attr "length" "4,8") (set_attr "type" "multi") - (set_attr "predicable" "no") - (set_attr "cond" "nocond")]) + (set_attr "predicable" "no") ]) (define_expand "umaddsidi4" [(match_operand:DI 0 "register_operand" "") @@ -6664,8 +6471,7 @@ archs4x, archs4xd" "macdu\\t%0,%1,%2" [(set_attr "length" "4,4,8") (set_attr "type" "multi") - (set_attr "predicable" "yes,no,no") - (set_attr "cond" "canuse,nocond,nocond")]) + (set_attr "predicable" "yes,no,no") ]) (define_insn "macu" [(set (reg:DI ARCV2_ACC) @@ -6677,8 +6483,7 @@ archs4x, archs4xd" "macu 0,%0,%1" [(set_attr "length" "4,8") (set_attr "type" "multi") - (set_attr "predicable" "no") - (set_attr "cond" "nocond")]) + (set_attr "predicable" "no") ]) (define_peephole2 [(set (reg:DI ARCV2_ACC) @@ -6707,8 +6512,7 @@ archs4x, archs4xd" "macu\\t%0,%1,%2" [(set_attr "length" "4,8") (set_attr "type" "multi") - (set_attr "predicable" "no") - (set_attr "cond" "nocond")]) + (set_attr "predicable" "no") ]) (define_insn "mpyd<su_optab>_arcv2hs" [(set (match_operand:DI 0 "even_register_operand" "=r") @@ -6779,8 +6583,7 @@ archs4x, archs4xd" "add%2%?\\t%0,%3,%1" [(set_attr "length" "*,4,8") (set_attr "predicable" "yes,no,no") - (set_attr "iscompact" "maybe,false,false") - (set_attr "cond" "canuse,nocond,nocond")]) + (set_attr "iscompact" "maybe,false,false") ]) (define_insn "*add_shift2" [(set (match_operand:SI 0 "register_operand" "=q,r,r") @@ -6791,8 +6594,7 @@ archs4x, archs4xd" "add%3%?\\t%0,%1,%2" [(set_attr "length" "*,4,8") (set_attr "predicable" "yes,no,no") - (set_attr "iscompact" "maybe,false,false") - (set_attr "cond" "canuse,nocond,nocond")]) + (set_attr "iscompact" "maybe,false,false") ]) (define_insn "*sub_shift" [(set (match_operand:SI 0"register_operand" "=r,r,r") @@ -6802,7 +6604,6 @@ archs4x, archs4xd" "" "sub%3\\t%0,%1,%2" [(set_attr "length" "4,4,8") - (set_attr "cond" "canuse,nocond,nocond") (set_attr "predicable" "yes,no,no")]) (define_insn "*sub_shift_cmp0_noout" diff --git a/gcc/config/arc/fpu.md b/gcc/config/arc/fpu.md index 14ebd865206e..c3fe1d0fd807 100644 --- a/gcc/config/arc/fpu.md +++ b/gcc/config/arc/fpu.md @@ -17,7 +17,6 @@ (set_attr "iscompact" "false") (set_attr "type" "fpu") (set_attr "predicable" "yes,no,no,yes,no,no") - (set_attr "cond" "canuse,nocond,nocond,canuse_limm,nocond,nocond") ]) ;; Subtraction @@ -33,7 +32,6 @@ (set_attr "iscompact" "false") (set_attr "type" "fpu") (set_attr "predicable" "yes,no,no,yes,no,no") - (set_attr "cond" "canuse,nocond,nocond,canuse_limm,nocond,nocond") ]) ;; Multiplication @@ -49,7 +47,6 @@ (set_attr "iscompact" "false") (set_attr "type" "fpu") (set_attr "predicable" "yes,no,yes,no,no") - (set_attr "cond" "canuse,nocond,canuse_limm,nocond,nocond") ]) ;; Multiplication with addition/subtraction @@ -96,7 +93,6 @@ "fsmadd%? %0,%1,%2" [(set_attr "length" "4,4,8,8,8") (set_attr "predicable" "yes,no,yes,no,no") - (set_attr "cond" "canuse,nocond,canuse_limm,nocond,nocond") (set_attr "iscompact" "false") (set_attr "type" "fpu_fuse")]) @@ -111,7 +107,6 @@ "fsmsub%?\\t%0,%1,%2" [(set_attr "length" "4,4,8,8,8") (set_attr "predicable" "yes,no,yes,no,no") - (set_attr "cond" "canuse,nocond,canuse_limm,nocond,nocond") (set_attr "iscompact" "false") (set_attr "type" "fpu_fuse")]) @@ -181,7 +176,6 @@ "fdmadd%?\\t%0,%1,%2" [(set_attr "length" "4,4") (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond") (set_attr "iscompact" "false") (set_attr "type" "fpu_fuse")]) @@ -194,7 +188,6 @@ "fdmsub%?\\t%0,%1,%2" [(set_attr "length" "4,4") (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond") (set_attr "iscompact" "false") (set_attr "type" "fpu_fuse")]) @@ -211,7 +204,6 @@ (set_attr "iscompact" "false") (set_attr "type" "fpu_sdiv") (set_attr "predicable" "yes,no,yes,no,no") - (set_attr "cond" "canuse,nocond,canuse_limm,nocond,nocond") ]) ;; Negation @@ -238,7 +230,6 @@ "fscmp%?\\t%0,%1" [(set_attr "length" "4,4,8") (set_attr "iscompact" "false") - (set_attr "cond" "set") (set_attr "type" "fpu") (set_attr "predicable" "yes")]) @@ -250,7 +241,6 @@ "fscmpf%?\\t%0,%1" [(set_attr "length" "4,4,8") (set_attr "iscompact" "false") - (set_attr "cond" "set") (set_attr "type" "fpu") (set_attr "predicable" "yes")]) @@ -263,7 +253,6 @@ "fscmp\\t%0,%1\\n\\tmov.v.f\\t0,0\\t;set Z flag" [(set_attr "length" "8,8,12") (set_attr "iscompact" "false") - (set_attr "cond" "set") (set_attr "type" "fpu")]) ;; :::::::::::::::::::: @@ -283,7 +272,6 @@ (set_attr "iscompact" "false") (set_attr "type" "fpu") (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond") ]) ;; Subtraction @@ -297,7 +285,6 @@ (set_attr "iscompact" "false") (set_attr "type" "fpu") (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond") ]) ;; Multiplication @@ -311,7 +298,6 @@ (set_attr "iscompact" "false") (set_attr "type" "fpu") (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond") ]) ;; Division @@ -325,7 +311,6 @@ (set_attr "iscompact" "false") (set_attr "type" "fpu_ddiv") (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond") ]) ;; Square root @@ -346,7 +331,6 @@ "fdcmp%? %0, %1" [(set_attr "length" "4") (set_attr "iscompact" "false") - (set_attr "cond" "set") (set_attr "type" "fpu") (set_attr "predicable" "yes")]) @@ -358,7 +342,6 @@ "fdcmpf%? %0, %1" [(set_attr "length" "4") (set_attr "iscompact" "false") - (set_attr "cond" "set") (set_attr "type" "fpu") (set_attr "predicable" "yes")]) @@ -371,7 +354,6 @@ "fdcmp %0, %1\\n\\tmov.v.f 0,0\\t;set Z flag" [(set_attr "length" "8") (set_attr "iscompact" "false") - (set_attr "cond" "set") (set_attr "type" "fpu")]) ;; :::::::::::::::::::: diff --git a/gcc/config/arc/fpx.md b/gcc/config/arc/fpx.md index 29c70e6a715e..dabff8f92c5b 100644 --- a/gcc/config/arc/fpx.md +++ b/gcc/config/arc/fpx.md @@ -634,9 +634,7 @@ "TARGET_FPX_QUARK" "dsp_fp_cmp\\t%2,%0,%1\\n\\trsub.f\\t0,%2,7\\n\\tcmp.nc\\t%2,1\\n\\tcmp.hi\\t%2,3" [(set_attr "length" "16") - (set_attr "cond" "set") - (set_attr "predicable" "no") - (set_attr "cond" "nocond")]) + (set_attr "predicable" "no") ]) (define_insn "*cmpsf_quark_ord" [(set (reg:CC_FP_ORD CC_REG) @@ -646,9 +644,7 @@ "TARGET_FPX_QUARK" "dsp_fp_cmp\\t%2,%0,%1\\n\\tadd.f\\t%2,%2,-8" [(set_attr "length" "8") - (set_attr "cond" "set") - (set_attr "predicable" "no") - (set_attr "cond" "nocond")]) + (set_attr "predicable" "no") ]) (define_insn "*cmpsf_quark_uneq" [(set (reg:CC_FP_UNEQ CC_REG) @@ -658,9 +654,7 @@ "TARGET_FPX_QUARK" "dsp_fp_cmp\\t%2,%0,%1\\n\\ttst\\t%2,6" [(set_attr "length" "8") - (set_attr "cond" "set") - (set_attr "predicable" "no") - (set_attr "cond" "nocond")]) + (set_attr "predicable" "no") ]) (define_insn "*cmpsf_quark_eq" [(set (reg:CC_Z CC_REG) @@ -670,9 +664,7 @@ "TARGET_FPX_QUARK" "dsp_fp_cmp\\t%2,%0,%1\\n\\ttst\\t%2,0x0E" [(set_attr "length" "8") - (set_attr "cond" "set") - (set_attr "predicable" "no") - (set_attr "cond" "nocond")]) + (set_attr "predicable" "no") ]) (define_insn "*divsf3_quark" [(set (match_operand:SF 0 "register_operand" "=r") @@ -681,8 +673,7 @@ "TARGET_FPX_QUARK" "dsp_fp_div\\t%0,%1,%2" [(set_attr "length" "4") - (set_attr "predicable" "no") - (set_attr "cond" "nocond")]) + (set_attr "predicable" "no") ]) (define_insn "*sqrtsf2_quark" [(set (match_operand:SF 0 "register_operand" "=r") @@ -690,8 +681,7 @@ "TARGET_FPX_QUARK" "dsp_fp_sqrt\\t%0,%1" [(set_attr "length" "4") - (set_attr "predicable" "no") - (set_attr "cond" "nocond")]) + (set_attr "predicable" "no") ]) ;; SF->SI (using rounding towards zero) (define_insn "*fix_truncsfsi2_quark" @@ -700,8 +690,7 @@ "TARGET_FPX_QUARK" "dsp_fp_flt2i\\t%0,%1" [(set_attr "length" "4") - (set_attr "predicable" "no") - (set_attr "cond" "nocond")]) + (set_attr "predicable" "no") ]) ;; SI->SF (define_insn "*floatsisf2_quark" @@ -710,6 +699,5 @@ "TARGET_FPX_QUARK" "dsp_fp_i2flt\\t%0,%1" [(set_attr "length" "4") - (set_attr "predicable" "no") - (set_attr "cond" "nocond")]) + (set_attr "predicable" "no") ]) diff --git a/gcc/config/arc/simdext.md b/gcc/config/arc/simdext.md index 003f2c4e6e60..15996a1d9712 100644 --- a/gcc/config/arc/simdext.md +++ b/gcc/config/arc/simdext.md @@ -176,8 +176,7 @@ "TARGET_SIMD_SET" "vld128\\t%0,[i%2,%3]" [(set_attr "type" "simd_vload128") - (set_attr "length" "4") - (set_attr "cond" "nocond")] + (set_attr "length" "4") ] ) (define_insn "vst128_insn" @@ -188,8 +187,7 @@ "TARGET_SIMD_SET" "vst128\\t%3,[i%1,%2]" [(set_attr "type" "simd_vstore") - (set_attr "length" "4") - (set_attr "cond" "nocond")] + (set_attr "length" "4") ] ) (define_insn "vst64_insn" @@ -206,8 +204,7 @@ "TARGET_SIMD_SET" "vst64\\t%3,[i%1,%2]" [(set_attr "type" "simd_vstore") - (set_attr "length" "4") - (set_attr "cond" "nocond")] + (set_attr "length" "4") ] ) (define_insn "movv8hi_insn" @@ -219,8 +216,7 @@ vst128r\\t%1,%0 vmvzw\\t%0,%1,0xffff" [(set_attr "type" "simd_vload128,simd_vstore,simd_vmove_else_zero") - (set_attr "length" "8,8,4") - (set_attr "cond" "nocond, nocond, nocond")]) + (set_attr "length" "8,8,4") ]) (define_insn "movti_insn" [(set (match_operand:TI 0 "vector_register_or_memory_operand" "=v,m,v") @@ -231,8 +227,7 @@ vst128r\\t%1,%0 vmvzw\\t%0,%1,0xffff" [(set_attr "type" "simd_vload128,simd_vstore,simd_vmove_else_zero") - (set_attr "length" "8,8,4") - (set_attr "cond" "nocond, nocond, nocond")]) + (set_attr "length" "8,8,4") ]) ;; V V V Insns (define_insn "vaddaw_insn" @@ -243,8 +238,7 @@ "TARGET_SIMD_SET" "vaddaw\\t%0,%1,%2" [(set_attr "type" "simd_varith_with_acc") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vaddw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -254,8 +248,7 @@ "TARGET_SIMD_SET" "vaddw\\t%0,%1,2" [(set_attr "type" "simd_varith_1cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vavb_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -265,8 +258,7 @@ "TARGET_SIMD_SET" "vavb\\t%0,%1,%2" [(set_attr "type" "simd_varith_1cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vavrb_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -276,8 +268,7 @@ "TARGET_SIMD_SET" "vavrb\\t%0,%1,%2" [(set_attr "type" "simd_varith_1cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vdifaw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -287,8 +278,7 @@ "TARGET_SIMD_SET" "vdifaw\\t%0,%1,%2" [(set_attr "type" "simd_varith_with_acc") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vdifw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -298,8 +288,7 @@ "TARGET_SIMD_SET" "vdifw\\t%0,%1,%2" [(set_attr "type" "simd_varith_1cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vmaxaw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -309,8 +298,7 @@ "TARGET_SIMD_SET" "vmaxaw\\t%0,%1,2" [(set_attr "type" "simd_varith_with_acc") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vmaxw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -320,8 +308,7 @@ "TARGET_SIMD_SET" "vmaxw\\t%0,%1,%2" [(set_attr "type" "simd_varith_1cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vminaw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -331,8 +318,7 @@ "TARGET_SIMD_SET" "vminaw\\t%0,%1,%2" [(set_attr "type" "simd_varith_with_acc") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vminw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -342,8 +328,7 @@ "TARGET_SIMD_SET" "vminw\\t%0,%1,%2" [(set_attr "type" "simd_varith_1cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vmulaw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -353,8 +338,7 @@ "TARGET_SIMD_SET" "vmulaw\\t%0,%1,%2" [(set_attr "type" "simd_varith_with_acc") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vmulfaw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -364,8 +348,7 @@ "TARGET_SIMD_SET" "vmulfaw\\t%0,%1,%2" [(set_attr "type" "simd_varith_with_acc") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vmulfw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -375,8 +358,7 @@ "TARGET_SIMD_SET" "vmulfw\\t%0,%1,%2" [(set_attr "type" "simd_varith_2cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vmulw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -386,8 +368,7 @@ "TARGET_SIMD_SET" "vmulw\\t%0,%1,%2" [(set_attr "type" "simd_varith_2cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vsubaw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -397,8 +378,7 @@ "TARGET_SIMD_SET" "vsubaw\\t%0,%1,%2" [(set_attr "type" "simd_varith_with_acc") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vsubw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -408,8 +388,7 @@ "TARGET_SIMD_SET" "vsubw\\t%0,%1,%2" [(set_attr "type" "simd_varith_1cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vsummw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -419,8 +398,7 @@ "TARGET_SIMD_SET" "vsummw\\t%0,%1,%2" [(set_attr "type" "simd_varith_2cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vand_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -430,8 +408,7 @@ "TARGET_SIMD_SET" "vand\\t%0,%1,%2" [(set_attr "type" "simd_vlogic") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vandaw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -441,8 +418,7 @@ "TARGET_SIMD_SET" "vandaw\\t%0,%1,%2" [(set_attr "type" "simd_vlogic_with_acc") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vbic_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -452,8 +428,7 @@ "TARGET_SIMD_SET" "vbic\\t%0,%1,%2" [(set_attr "type" "simd_vlogic") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vbicaw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -463,8 +438,7 @@ "TARGET_SIMD_SET" "vbicaw\\t%0,%1,%2" [(set_attr "type" "simd_vlogic_with_acc") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vor_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -474,8 +448,7 @@ "TARGET_SIMD_SET" "vor\\t%0,%1,%2" [(set_attr "type" "simd_vlogic") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vxor_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -485,8 +458,7 @@ "TARGET_SIMD_SET" "vxor\\t%0,%1,%2" [(set_attr "type" "simd_vlogic") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vxoraw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -496,8 +468,7 @@ "TARGET_SIMD_SET" "vxoraw\\t%0,%1,%2" [(set_attr "type" "simd_vlogic_with_acc") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "veqw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -507,8 +478,7 @@ "TARGET_SIMD_SET" "veqw\\t%0,%1,%2" [(set_attr "type" "simd_vcompare") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vlew_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -518,8 +488,7 @@ "TARGET_SIMD_SET" "vlew\\t%0,%1,%2" [(set_attr "type" "simd_vcompare") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vltw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -529,8 +498,7 @@ "TARGET_SIMD_SET" "vltw\\t%0,%1,%2" [(set_attr "type" "simd_vcompare") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vnew_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -540,8 +508,7 @@ "TARGET_SIMD_SET" "vnew\\t%0,%1,%2" [(set_attr "type" "simd_vcompare") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vmr1aw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -551,8 +518,7 @@ "TARGET_SIMD_SET" "vmr1aw\\t%0,%1,%2" [(set_attr "type" "simd_valign_with_acc") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vmr1w_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -562,8 +528,7 @@ "TARGET_SIMD_SET" "vmr1w\\t%0,%1,%2" [(set_attr "type" "simd_valign") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vmr2aw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -573,8 +538,7 @@ "TARGET_SIMD_SET" "vmr2aw\\t%0,%1,%2" [(set_attr "type" "simd_valign_with_acc") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vmr2w_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -584,8 +548,7 @@ "TARGET_SIMD_SET" "vmr2w\\t%0,%1,%2" [(set_attr "type" "simd_valign") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vmr3aw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -595,8 +558,7 @@ "TARGET_SIMD_SET" "vmr3aw\\t%0,%1,%2" [(set_attr "type" "simd_valign_with_acc") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vmr3w_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -606,8 +568,7 @@ "TARGET_SIMD_SET" "vmr3w\\t%0,%1,%2" [(set_attr "type" "simd_valign") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vmr4aw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -617,8 +578,7 @@ "TARGET_SIMD_SET" "vmr4aw\\t%0,%1,%2" [(set_attr "type" "simd_valign_with_acc") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vmr4w_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -628,8 +588,7 @@ "TARGET_SIMD_SET" "vmr4w\\t%0,%1,%2" [(set_attr "type" "simd_valign") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vmr5aw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -639,8 +598,7 @@ "TARGET_SIMD_SET" "vmr5aw\\t%0,%1,%2" [(set_attr "type" "simd_valign_with_acc") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vmr5w_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -650,8 +608,7 @@ "TARGET_SIMD_SET" "vmr5w\\t%0,%1,%2" [(set_attr "type" "simd_valign") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vmr6aw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -661,8 +618,7 @@ "TARGET_SIMD_SET" "vmr6aw\\t%0,%1,%2" [(set_attr "type" "simd_valign_with_acc") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vmr6w_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -672,8 +628,7 @@ "TARGET_SIMD_SET" "vmr6w\\t%0,%1,%2" [(set_attr "type" "simd_valign") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vmr7aw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -683,8 +638,7 @@ "TARGET_SIMD_SET" "vmr7aw\\t%0,%1,%2" [(set_attr "type" "simd_valign_with_acc") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vmr7w_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -694,8 +648,7 @@ "TARGET_SIMD_SET" "vmr7w\\t%0,%1,%2" [(set_attr "type" "simd_valign") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vmrb_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -705,8 +658,7 @@ "TARGET_SIMD_SET" "vmrb\\t%0,%1,%2" [(set_attr "type" "simd_valign") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vh264f_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -716,8 +668,7 @@ "TARGET_SIMD_SET" "vh264f\\t%0,%1,%2" [(set_attr "type" "simd_vspecial_3cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vh264ft_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -727,8 +678,7 @@ "TARGET_SIMD_SET" "vh264ft\\t%0,%1,%2" [(set_attr "type" "simd_vspecial_3cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vh264fw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -738,8 +688,7 @@ "TARGET_SIMD_SET" "vh264fw\\t%0,%1,%2" [(set_attr "type" "simd_vspecial_3cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vvc1f_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -749,8 +698,7 @@ "TARGET_SIMD_SET" "vvc1f\\t%0,%1,%2" [(set_attr "type" "simd_vspecial_3cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vvc1ft_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -760,8 +708,7 @@ "TARGET_SIMD_SET" "vvc1ft\\t%0,%1,%2" [(set_attr "type" "simd_vspecial_3cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) @@ -775,8 +722,7 @@ "TARGET_SIMD_SET" "vbaddw\\t%0,%1,%2" [(set_attr "type" "simd_varith_1cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vbmaxw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -786,8 +732,7 @@ "TARGET_SIMD_SET" "vbmaxw\\t%0,%1,%2" [(set_attr "type" "simd_varith_1cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vbminw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -797,8 +742,7 @@ "TARGET_SIMD_SET" "vbminw\\t%0,%1,%2" [(set_attr "type" "simd_varith_1cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vbmulaw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -808,8 +752,7 @@ "TARGET_SIMD_SET" "vbmulaw\\t%0,%1,%2" [(set_attr "type" "simd_varith_with_acc") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vbmulfw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -819,8 +762,7 @@ "TARGET_SIMD_SET" "vbmulfw\\t%0,%1,%2" [(set_attr "type" "simd_varith_2cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vbmulw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -830,8 +772,7 @@ "TARGET_SIMD_SET" "vbmulw\\t%0,%1,%2" [(set_attr "type" "simd_varith_2cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vbrsubw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -841,8 +782,7 @@ "TARGET_SIMD_SET" "vbrsubw\\t%0,%1,%2" [(set_attr "type" "simd_varith_1cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vbsubw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -852,8 +792,7 @@ "TARGET_SIMD_SET" "vbsubw\\t%0,%1,%2" [(set_attr "type" "simd_varith_1cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) ; Va, Vb, Ic instructions ; Va, Vb, u6 instructions @@ -865,8 +804,7 @@ "TARGET_SIMD_SET" "vasrrwi\\t%0,%1,%2" [(set_attr "type" "simd_varith_2cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vasrsrwi_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -876,8 +814,7 @@ "TARGET_SIMD_SET" "vasrsrwi\\t%0,%1,%2" [(set_attr "type" "simd_varith_2cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vasrwi_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -887,8 +824,7 @@ "TARGET_SIMD_SET" "vasrwi\\t%0,%1,%2" [(set_attr "type" "simd_varith_1cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vasrpwbi_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -898,8 +834,7 @@ "TARGET_SIMD_SET" "vasrpwbi\\t%0,%1,%2" [(set_attr "type" "simd_vpack") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vasrrpwbi_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -909,8 +844,7 @@ "TARGET_SIMD_SET" "vasrrpwbi\\t%0,%1,%2" [(set_attr "type" "simd_vpack") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vsr8awi_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -920,8 +854,7 @@ "TARGET_SIMD_SET" "vsr8awi\\t%0,%1,%2" [(set_attr "type" "simd_valign_with_acc") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vsr8i_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -931,8 +864,7 @@ "TARGET_SIMD_SET" "vsr8i\\t%0,%1,%2" [(set_attr "type" "simd_valign") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) ;; Va, Vb, u8 (simm) insns @@ -944,8 +876,7 @@ "TARGET_SIMD_SET" "vmvaw\\t%0,%1,%2" [(set_attr "type" "simd_vmove_with_acc") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vmvw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -955,8 +886,7 @@ "TARGET_SIMD_SET" "vmvw\\t%0,%1,%2" [(set_attr "type" "simd_vmove") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vmvzw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -966,8 +896,7 @@ "TARGET_SIMD_SET" "vmvzw\\t%0,%1,%2" [(set_attr "type" "simd_vmove_else_zero") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vd6tapf_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -977,8 +906,7 @@ "TARGET_SIMD_SET" "vd6tapf\\t%0,%1,%2" [(set_attr "type" "simd_vspecial_4cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) ;; Va, rlimm, u8 (simm) insns (define_insn "vmovaw_insn" @@ -989,8 +917,7 @@ "TARGET_SIMD_SET" "vmovaw\\t%0,%1,%2" [(set_attr "type" "simd_vmove_with_acc") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vmovw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -1000,8 +927,7 @@ "TARGET_SIMD_SET" "vmovw\\t%0,%1,%2" [(set_attr "type" "simd_vmove") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vmovzw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -1011,8 +937,7 @@ "TARGET_SIMD_SET" "vmovzw\\t%0,%1,%2" [(set_attr "type" "simd_vmove_else_zero") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) ;; Va, rlimm, Ic insns (define_insn "vsr8_insn" @@ -1024,8 +949,7 @@ "TARGET_SIMD_SET" "vsr8\\t%0,%1,i%2" [(set_attr "type" "simd_valign") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vasrw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -1036,8 +960,7 @@ "TARGET_SIMD_SET" "vasrw\\t%0,%1,i%2" [(set_attr "type" "simd_varith_1cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vsr8aw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -1048,8 +971,7 @@ "TARGET_SIMD_SET" "vsr8aw\\t%0,%1,i%2" [(set_attr "type" "simd_valign_with_acc") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) ;; Va, Vb insns (define_insn "vabsaw_insn" @@ -1059,8 +981,7 @@ "TARGET_SIMD_SET" "vabsaw\\t%0,%1" [(set_attr "type" "simd_varith_with_acc") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vabsw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -1069,8 +990,7 @@ "TARGET_SIMD_SET" "vabsw\\t%0,%1" [(set_attr "type" "simd_varith_1cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vaddsuw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -1079,8 +999,7 @@ "TARGET_SIMD_SET" "vaddsuw\\t%0,%1" [(set_attr "type" "simd_varith_1cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vsignw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -1089,8 +1008,7 @@ "TARGET_SIMD_SET" "vsignw\\t%0,%1" [(set_attr "type" "simd_varith_1cycle") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vexch1_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -1099,8 +1017,7 @@ "TARGET_SIMD_SET" "vexch1\\t%0,%1" [(set_attr "type" "simd_vpermute") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vexch2_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -1109,8 +1026,7 @@ "TARGET_SIMD_SET" "vexch2\\t%0,%1" [(set_attr "type" "simd_vpermute") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vexch4_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -1119,8 +1035,7 @@ "TARGET_SIMD_SET" "vexch4\\t%0,%1" [(set_attr "type" "simd_vpermute") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vupbaw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -1129,8 +1044,7 @@ "TARGET_SIMD_SET" "vupbaw\\t%0,%1" [(set_attr "type" "simd_vpack_with_acc") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vupbw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -1139,8 +1053,7 @@ "TARGET_SIMD_SET" "vupbw\\t%0,%1" [(set_attr "type" "simd_vpack") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vupsbaw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -1149,8 +1062,7 @@ "TARGET_SIMD_SET" "vupsbaw\\t%0,%1" [(set_attr "type" "simd_vpack_with_acc") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vupsbw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -1159,8 +1071,7 @@ "TARGET_SIMD_SET" "vupsbw\\t%0,%1" [(set_attr "type" "simd_vpack") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) ; DMA setup instructions (define_insn "vdirun_insn" @@ -1171,8 +1082,7 @@ "TARGET_SIMD_SET" "vdirun\\t%1,%2" [(set_attr "type" "simd_dma") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vdorun_insn" [(set (match_operand:SI 0 "arc_simd_dma_register_operand" "=d") @@ -1182,8 +1092,7 @@ "TARGET_SIMD_SET" "vdorun\\t%1,%2" [(set_attr "type" "simd_dma") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vdiwr_insn" [(set (match_operand:SI 0 "arc_simd_dma_register_operand" "=d,d") @@ -1192,8 +1101,7 @@ "TARGET_SIMD_SET" "vdiwr\\t%0,%1" [(set_attr "type" "simd_dma") - (set_attr "length" "4,8") - (set_attr "cond" "nocond,nocond")]) + (set_attr "length" "4,8") ]) (define_insn "vdowr_insn" [(set (match_operand:SI 0 "arc_simd_dma_register_operand" "=d,d") @@ -1202,8 +1110,7 @@ "TARGET_SIMD_SET" "vdowr\\t%0,%1" [(set_attr "type" "simd_dma") - (set_attr "length" "4,8") - (set_attr "cond" "nocond,nocond")]) + (set_attr "length" "4,8") ]) ;; vector record and run instructions (define_insn "vrec_insn" @@ -1212,8 +1119,7 @@ "TARGET_SIMD_SET" "vrec\\t%0" [(set_attr "type" "simd_vcontrol") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vrun_insn" [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "r")] @@ -1221,8 +1127,7 @@ "TARGET_SIMD_SET" "vrun\\t%0" [(set_attr "type" "simd_vcontrol") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vrecrun_insn" [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "r")] @@ -1230,8 +1135,7 @@ "TARGET_SIMD_SET" "vrecrun\\t%0" [(set_attr "type" "simd_vcontrol") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vendrec_insn" [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "r")] @@ -1239,8 +1143,7 @@ "TARGET_SIMD_SET" "vendrec\\t%0" [(set_attr "type" "simd_vcontrol") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vld32wh_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -1260,8 +1163,7 @@ "TARGET_SIMD_SET" "vld32wh\\t%0,[i%3,%1]" [(set_attr "type" "simd_vload") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vld32wl_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -1281,8 +1183,7 @@ "TARGET_SIMD_SET" "vld32wl\\t%0,[i%3,%1]" [(set_attr "type" "simd_vload") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vld64w_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -1296,8 +1197,7 @@ "TARGET_SIMD_SET" "vld64w\\t%0,[i%2,%3]" [(set_attr "type" "simd_vload") - (set_attr "length" "4") - (set_attr "cond" "nocond")] + (set_attr "length" "4") ] ) (define_insn "vld64_insn" @@ -1317,8 +1217,7 @@ "TARGET_SIMD_SET" "vld64\\t%0,[i%3,%1]" [(set_attr "type" "simd_vload") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vld32_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") @@ -1340,8 +1239,7 @@ "TARGET_SIMD_SET" "vld32\\t%0,[i%3,%1]" [(set_attr "type" "simd_vload") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vst16_n_insn" [(set (mem:HI @@ -1355,8 +1253,7 @@ "TARGET_SIMD_SET" "vst16_%4\\t%3,[i%2,%0]" [(set_attr "type" "simd_vstore") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) (define_insn "vst32_n_insn" [(set (mem:SI @@ -1371,8 +1268,7 @@ "TARGET_SIMD_SET" "vst32_%4\\t%3,[i%2,%0]" [(set_attr "type" "simd_vstore") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) ;; SIMD unit interrupt (define_insn "vinti_insn" @@ -1381,8 +1277,7 @@ "TARGET_SIMD_SET" "vinti\\t%0" [(set_attr "type" "simd_vcontrol") - (set_attr "length" "4") - (set_attr "cond" "nocond")]) + (set_attr "length" "4") ]) ;; New ARCv2 SIMD extensions @@ -1516,8 +1411,7 @@ "vadd<V_suffix>%?\\t%0,%1,%2" [(set_attr "length" "4") (set_attr "type" "multi") - (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond")]) + (set_attr "predicable" "yes,no") ]) (define_insn "sub<mode>3" [(set (match_operand:VCT 0 "register_operand" "=r,r") @@ -1527,8 +1421,7 @@ "vsub<V_suffix>%?\\t%0,%1,%2" [(set_attr "length" "4") (set_attr "type" "multi") - (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond")]) + (set_attr "predicable" "yes,no") ]) ;; Combined arithmetic ops (define_insn "addsub<mode>3" @@ -1546,8 +1439,7 @@ "vaddsub<V_addsub_suffix>%?\\t%0,%1,%2" [(set_attr "length" "4") (set_attr "type" "multi") - (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond")]) + (set_attr "predicable" "yes,no") ]) (define_insn "subadd<mode>3" [(set (match_operand:VDV 0 "register_operand" "=r,r") @@ -1564,8 +1456,7 @@ "vsubadd<V_addsub_suffix>%?\\t%0,%1,%2" [(set_attr "length" "4") (set_attr "type" "multi") - (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond")]) + (set_attr "predicable" "yes,no") ]) (define_insn "addsubv4hi3" [(set (match_operand:V4HI 0 "even_register_operand" "=r,r") @@ -1588,8 +1479,7 @@ "vaddsub4h%?\\t%0,%1,%2" [(set_attr "length" "4") (set_attr "type" "multi") - (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond")]) + (set_attr "predicable" "yes,no") ]) (define_insn "subaddv4hi3" [(set (match_operand:V4HI 0 "even_register_operand" "=r,r") @@ -1612,8 +1502,7 @@ "vsubadd4h%?\\t%0,%1,%2" [(set_attr "length" "4") (set_attr "type" "multi") - (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond")]) + (set_attr "predicable" "yes,no") ]) ;; Multiplication (define_insn "dmpyh<V_US_suffix>" @@ -1642,8 +1531,7 @@ "dmpyh<V_US_suffix>%?\\t%0,%1,%2" [(set_attr "length" "4") (set_attr "type" "multi") - (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond")]) + (set_attr "predicable" "yes,no") ]) ;; We can use dmac as well here. To be investigated which version ;; brings more. @@ -1731,8 +1619,7 @@ "vmpy2h<V_US_suffix>%?\\t%0,%1,%2" [(set_attr "length" "4") (set_attr "type" "multi") - (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond")]) + (set_attr "predicable" "yes,no") ]) (define_insn "arc_vec_<V_US>multacc_lo_v4hi" [(set (reg:V2SI ARCV2_ACC) @@ -1747,8 +1634,7 @@ "vmpy2h<V_US_suffix>%?\\t0,%0,%1" [(set_attr "length" "4") (set_attr "type" "multi") - (set_attr "predicable" "no") - (set_attr "cond" "nocond")]) + (set_attr "predicable" "no") ]) (define_expand "vec_widen_<V_US>mult_lo_v4hi" [(set (match_operand:V2SI 0 "even_register_operand" "") @@ -1787,8 +1673,7 @@ "vmpy2h<V_US_suffix>%?\\t%0,%R1,%R2" [(set_attr "length" "4") (set_attr "type" "multi") - (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond")]) + (set_attr "predicable" "yes,no") ]) (define_expand "vec_widen_<V_US>mult_hi_v4hi" [(set (match_operand:V2SI 0 "even_register_operand") @@ -1852,8 +1737,7 @@ "dmach%?\\t%0,%1,%2" [(set_attr "length" "4") (set_attr "type" "multi") - (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond")]) + (set_attr "predicable" "yes,no") ]) (define_insn "dmachu" [(set (match_operand:SI 0 "register_operand" "=r,r") @@ -1866,8 +1750,7 @@ "dmachu%?\\t%0,%1,%2" [(set_attr "length" "4") (set_attr "type" "multi") - (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond")]) + (set_attr "predicable" "yes,no") ]) (define_insn "dmacwh" [(set (match_operand:DI 0 "even_register_operand" "=r,r") @@ -1880,8 +1763,7 @@ "dmacwh%?\\t%0,%1,%2" [(set_attr "length" "4") (set_attr "type" "multi") - (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond")]) + (set_attr "predicable" "yes,no") ]) (define_insn "dmacwhu" [(set (match_operand:DI 0 "register_operand" "=r,r") @@ -1894,8 +1776,7 @@ "dmacwhu%?\\t%0,%1,%2" [(set_attr "length" "4") (set_attr "type" "multi") - (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond")]) + (set_attr "predicable" "yes,no") ]) (define_insn "vmac2h" [(set (match_operand:V2SI 0 "even_register_operand" "=r,r") @@ -1908,8 +1789,7 @@ "vmac2h%?\\t%0,%1,%2" [(set_attr "length" "4") (set_attr "type" "multi") - (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond")]) + (set_attr "predicable" "yes,no") ]) (define_insn "vmac2hu" [(set (match_operand:V2SI 0 "even_register_operand" "=r,r") @@ -1922,8 +1802,7 @@ "vmac2hu%?\\t%0,%1,%2" [(set_attr "length" "4") (set_attr "type" "multi") - (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond")]) + (set_attr "predicable" "yes,no") ]) (define_insn "vmpy2h" [(set (match_operand:V2SI 0 "even_register_operand" "=r,r") @@ -1935,8 +1814,7 @@ "vmpy2h%?\\t%0,%1,%2" [(set_attr "length" "4") (set_attr "type" "multi") - (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond")]) + (set_attr "predicable" "yes,no") ]) (define_insn "vmpy2hu" [(set (match_operand:V2SI 0 "even_register_operand" "=r,r") @@ -1948,8 +1826,7 @@ "vmpy2hu%?\\t%0,%1,%2" [(set_attr "length" "4") (set_attr "type" "multi") - (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond")]) + (set_attr "predicable" "yes,no") ]) (define_insn "qmach" [(set (match_operand:DI 0 "even_register_operand" "=r,r") @@ -1962,8 +1839,7 @@ "qmach%?\\t%0,%1,%2" [(set_attr "length" "4") (set_attr "type" "multi") - (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond")]) + (set_attr "predicable" "yes,no") ]) (define_insn "qmachu" [(set (match_operand:DI 0 "even_register_operand" "=r,r") @@ -1976,8 +1852,7 @@ "qmachu%?\\t%0,%1,%2" [(set_attr "length" "4") (set_attr "type" "multi") - (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond")]) + (set_attr "predicable" "yes,no") ]) (define_insn "qmpyh" [(set (match_operand:DI 0 "even_register_operand" "=r,r") @@ -1989,8 +1864,7 @@ "qmpyh%?\\t%0,%1,%2" [(set_attr "length" "4") (set_attr "type" "multi") - (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond")]) + (set_attr "predicable" "yes,no") ]) (define_insn "qmpyhu" [(set (match_operand:DI 0 "even_register_operand" "=r,r") @@ -2002,8 +1876,7 @@ "qmpyhu%?\\t%0,%1,%2" [(set_attr "length" "4") (set_attr "type" "multi") - (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond")]) + (set_attr "predicable" "yes,no") ]) ;; Emulated vector instructions. (define_insn_and_split "<voptab>v2si3"
