https://gcc.gnu.org/g:6da0b1468bfc4fbf4e8029b9dd634c31cb8261d8
commit r17-4382-g6da0b1468bfc4fbf4e8029b9dd634c31cb8261d8 Author: Michiel Derhaeg <[email protected]> Date: Thu Sep 17 11:38:06 2026 +0300 arc: Don't advertise optab for unsupported vector modes [PR126243] <voptab>v2si3 advertised V2SImode optabs (mul/div/smin/smax) whenever the scalar op existed, but V2SImode is only a supported vector mode under TARGET_PLUS_QMACW. Since r15-5493-g485ab50c204ddb ("Add helpers to test whether an optab can be implemented") the middle-end keeps the operation vectorized on such cores. The operands degrade to DImode and it is expanded as a double-word scalar op: mul and div silently compute on the packed pair, min and max ICE in expand_expr_real_2 for lack of a DImode expansion. Require TARGET_PLUS_QMACW so the optab matches arc_vector_mode_supported_p. No tests added because this is already covered by existing tests. PR target/126243 gcc/ChangeLog: * config/arc/simdext.md (<voptab>v2si3): Require TARGET_PLUS_QMACW. Signed-off-by: Michiel Derhaeg <[email protected]> Diff: --- gcc/config/arc/simdext.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/arc/simdext.md b/gcc/config/arc/simdext.md index 15996a1d9712..4f9bed795ab5 100644 --- a/gcc/config/arc/simdext.md +++ b/gcc/config/arc/simdext.md @@ -1883,7 +1883,7 @@ [(set (match_operand:V2SI 0 "register_operand" "=r") (EMUVEC:V2SI (match_operand:V2SI 1 "register_operand" "r") (match_operand:V2SI 2 "nonmemory_operand" "ri")))] - "" + "TARGET_PLUS_QMACW" "#" "reload_completed" [(const_int 0)]
