https://gcc.gnu.org/g:9c73440b6f8b81040379de62dc040aa8d2fd0803
commit r17-5607-g9c73440b6f8b81040379de62dc040aa8d2fd0803 Author: Pan Li <[email protected]> Date: Mon Oct 26 09:38:34 2026 +0800 RISC-V: Add more test cases for vfw{macc,msac}.vv For csrr not asm check when enable overlap enabled. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112431-61.c: New test. * gcc.target/riscv/rvv/base/pr112431-62.c: New test. Signed-off-by: Pan Li <[email protected]> Diff: --- .../gcc.target/riscv/rvv/base/pr112431-61.c | 59 ++++++++++++++++++++++ .../gcc.target/riscv/rvv/base/pr112431-62.c | 59 ++++++++++++++++++++++ 2 files changed, 118 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-61.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-61.c new file mode 100644 index 000000000000..74521b728034 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-61.c @@ -0,0 +1,59 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +void +foo (void *in, void *out, int n) +{ + for (int i = 0; i < n; i++) + { + asm volatile("nop" ::: "memory"); + vfloat64m4_t v0 = __riscv_vle64_v_f64m4 (in, 4);in+=100; + vfloat32m2_t v0_n = __riscv_vreinterpret_v_i32m2_f32m2 (__riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (__riscv_vget_v_f64m4_f64m2 (v0, 1)))); + v0 = __riscv_vfwmacc_vv_f64m4_tu (v0, v0_n, v0_n, 4); + asm volatile("nop" ::: "memory"); + vfloat64m4_t v1 = __riscv_vle64_v_f64m4 (in, 4);in+=100; + vfloat32m2_t v1_n = __riscv_vreinterpret_v_i32m2_f32m2 (__riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (__riscv_vget_v_f64m4_f64m2 (v1, 1)))); + v1 = __riscv_vfwmacc_vv_f64m4_tu (v1, v1_n, v1_n, 4); + asm volatile("nop" ::: "memory"); + vfloat64m4_t v2 = __riscv_vle64_v_f64m4 (in, 4);in+=100; + vfloat32m2_t v2_n = __riscv_vreinterpret_v_i32m2_f32m2 (__riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (__riscv_vget_v_f64m4_f64m2 (v2, 1)))); + v2 = __riscv_vfwmacc_vv_f64m4_tu (v2, v2_n, v2_n, 4); + asm volatile("nop" ::: "memory"); + vfloat64m4_t v3 = __riscv_vle64_v_f64m4 (in, 4);in+=100; + vfloat32m2_t v3_n = __riscv_vreinterpret_v_i32m2_f32m2 (__riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (__riscv_vget_v_f64m4_f64m2 (v3, 1)))); + v3 = __riscv_vfwmacc_vv_f64m4_tu (v3, v3_n, v3_n, 4); + asm volatile("nop" ::: "memory"); + vfloat64m4_t v4 = __riscv_vle64_v_f64m4 (in, 4);in+=100; + vfloat32m2_t v4_n = __riscv_vreinterpret_v_i32m2_f32m2 (__riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (__riscv_vget_v_f64m4_f64m2 (v4, 1)))); + v4 = __riscv_vfwmacc_vv_f64m4_tu (v4, v4_n, v4_n, 4); + asm volatile("nop" ::: "memory"); + vfloat64m4_t v5 = __riscv_vle64_v_f64m4 (in, 4);in+=100; + vfloat32m2_t v5_n = __riscv_vreinterpret_v_i32m2_f32m2 (__riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (__riscv_vget_v_f64m4_f64m2 (v5, 1)))); + v5 = __riscv_vfwmacc_vv_f64m4_tu (v5, v5_n, v5_n, 4); + asm volatile("nop" ::: "memory"); + vfloat64m4_t v6 = __riscv_vle64_v_f64m4 (in, 4);in+=100; + vfloat32m2_t v6_n = __riscv_vreinterpret_v_i32m2_f32m2 (__riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (__riscv_vget_v_f64m4_f64m2 (v6, 1)))); + v6 = __riscv_vfwmacc_vv_f64m4_tu (v6, v6_n, v6_n, 4); + asm volatile("nop" ::: "memory"); + vfloat32m2_t v7_n = __riscv_vle32_v_f32m2 (in, 4);in+=100; + vfloat64m4_t v7 = __riscv_vfwcvt_f_f_v_f64m4 (v7_n, 4); + + asm volatile("nop" ::: "memory"); + __riscv_vsse64_v_f64m4 (out, 8, v0, 4);out+=100; + __riscv_vsse64_v_f64m4 (out, 8, v1, 4);out+=100; + __riscv_vsse64_v_f64m4 (out, 8, v2, 4);out+=100; + __riscv_vsse64_v_f64m4 (out, 8, v3, 4);out+=100; + __riscv_vsse64_v_f64m4 (out, 8, v4, 4);out+=100; + __riscv_vsse64_v_f64m4 (out, 8, v5, 4);out+=100; + __riscv_vsse64_v_f64m4 (out, 8, v6, 4);out+=100; + __riscv_vsse64_v_f64m4 (out, 8, v7, 4);out+=100; + } +} + +/* { dg-final { scan-assembler-not {vmv1r} } } */ +/* { dg-final { scan-assembler-not {vmv2r} } } */ +/* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */ +/* { dg-final { scan-assembler-not {vmv8r} } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-62.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-62.c new file mode 100644 index 000000000000..8c7032cd8756 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-62.c @@ -0,0 +1,59 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +void +foo (void *in, void *out, int n) +{ + for (int i = 0; i < n; i++) + { + asm volatile("nop" ::: "memory"); + vfloat64m4_t v0 = __riscv_vle64_v_f64m4 (in, 4);in+=100; + vfloat32m2_t v0_n = __riscv_vreinterpret_v_i32m2_f32m2 (__riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (__riscv_vget_v_f64m4_f64m2 (v0, 1)))); + v0 = __riscv_vfwmsac_vv_f64m4_tu (v0, v0_n, v0_n, 4); + asm volatile("nop" ::: "memory"); + vfloat64m4_t v1 = __riscv_vle64_v_f64m4 (in, 4);in+=100; + vfloat32m2_t v1_n = __riscv_vreinterpret_v_i32m2_f32m2 (__riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (__riscv_vget_v_f64m4_f64m2 (v1, 1)))); + v1 = __riscv_vfwmsac_vv_f64m4_tu (v1, v1_n, v1_n, 4); + asm volatile("nop" ::: "memory"); + vfloat64m4_t v2 = __riscv_vle64_v_f64m4 (in, 4);in+=100; + vfloat32m2_t v2_n = __riscv_vreinterpret_v_i32m2_f32m2 (__riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (__riscv_vget_v_f64m4_f64m2 (v2, 1)))); + v2 = __riscv_vfwmsac_vv_f64m4_tu (v2, v2_n, v2_n, 4); + asm volatile("nop" ::: "memory"); + vfloat64m4_t v3 = __riscv_vle64_v_f64m4 (in, 4);in+=100; + vfloat32m2_t v3_n = __riscv_vreinterpret_v_i32m2_f32m2 (__riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (__riscv_vget_v_f64m4_f64m2 (v3, 1)))); + v3 = __riscv_vfwmsac_vv_f64m4_tu (v3, v3_n, v3_n, 4); + asm volatile("nop" ::: "memory"); + vfloat64m4_t v4 = __riscv_vle64_v_f64m4 (in, 4);in+=100; + vfloat32m2_t v4_n = __riscv_vreinterpret_v_i32m2_f32m2 (__riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (__riscv_vget_v_f64m4_f64m2 (v4, 1)))); + v4 = __riscv_vfwmsac_vv_f64m4_tu (v4, v4_n, v4_n, 4); + asm volatile("nop" ::: "memory"); + vfloat64m4_t v5 = __riscv_vle64_v_f64m4 (in, 4);in+=100; + vfloat32m2_t v5_n = __riscv_vreinterpret_v_i32m2_f32m2 (__riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (__riscv_vget_v_f64m4_f64m2 (v5, 1)))); + v5 = __riscv_vfwmsac_vv_f64m4_tu (v5, v5_n, v5_n, 4); + asm volatile("nop" ::: "memory"); + vfloat64m4_t v6 = __riscv_vle64_v_f64m4 (in, 4);in+=100; + vfloat32m2_t v6_n = __riscv_vreinterpret_v_i32m2_f32m2 (__riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (__riscv_vget_v_f64m4_f64m2 (v6, 1)))); + v6 = __riscv_vfwmsac_vv_f64m4_tu (v6, v6_n, v6_n, 4); + asm volatile("nop" ::: "memory"); + vfloat32m2_t v7_n = __riscv_vle32_v_f32m2 (in, 4);in+=100; + vfloat64m4_t v7 = __riscv_vfwcvt_f_f_v_f64m4 (v7_n, 4); + + asm volatile("nop" ::: "memory"); + __riscv_vsse64_v_f64m4 (out, 8, v0, 4);out+=100; + __riscv_vsse64_v_f64m4 (out, 8, v1, 4);out+=100; + __riscv_vsse64_v_f64m4 (out, 8, v2, 4);out+=100; + __riscv_vsse64_v_f64m4 (out, 8, v3, 4);out+=100; + __riscv_vsse64_v_f64m4 (out, 8, v4, 4);out+=100; + __riscv_vsse64_v_f64m4 (out, 8, v5, 4);out+=100; + __riscv_vsse64_v_f64m4 (out, 8, v6, 4);out+=100; + __riscv_vsse64_v_f64m4 (out, 8, v7, 4);out+=100; + } +} + +/* { dg-final { scan-assembler-not {vmv1r} } } */ +/* { dg-final { scan-assembler-not {vmv2r} } } */ +/* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */ +/* { dg-final { scan-assembler-not {vmv8r} } } */ +/* { dg-final { scan-assembler-not {csrr} } } */
