https://gcc.gnu.org/g:dafa6930eb51ef8ec9144c3747d741ce5cd2afeb
commit r17-5604-gdafa6930eb51ef8ec9144c3747d741ce5cd2afeb Author: Pan Li <[email protected]> Date: Sun Oct 25 21:06:05 2026 +0800 RISC-V: Allow RVV register overlap for vfw{macc,msac}.vv Like vwmacc.vv, allow the rvv register overlap for the dual widen float ternary vv insns, aka vfwmacc.vv and vfwmsac.vv. gcc/ChangeLog: * config/riscv/vector.md: Leverage Wvr constraint. Signed-off-by: Pan Li <[email protected]> Diff: --- gcc/config/riscv/vector.md | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 6b82620c61f4..f575e46084ee 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7428,25 +7428,25 @@ ;; ------------------------------------------------------------------------------- (define_insn "@pred_widen_mul_<optab><mode>" - [(set (match_operand:VWEXTF 0 "register_operand" "=&vr") + [(set (match_operand:VWEXTF 0 "register_operand" "=vr, vd") (if_then_else:VWEXTF (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1") - (match_operand 5 "vector_length_operand" " rvl") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (match_operand 8 "const_int_operand" " i") - (match_operand 9 "const_int_operand" " i") + [(match_operand:<VM> 1 "vector_mask_operand" "Wc1, vm") + (match_operand 5 "vector_length_operand" "rvl,rvl") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (match_operand 9 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VWEXTF (mult:VWEXTF (float_extend:VWEXTF - (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr")) + (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "Wvr,Wvr")) (float_extend:VWEXTF - (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))) - (match_operand:VWEXTF 2 "register_operand" " 0")) + (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "Wvr,Wvr"))) + (match_operand:VWEXTF 2 "register_operand" " 0, 0")) (match_dup 2)))] "TARGET_VECTOR" "vfw<macc_msac>.vv\t%0,%3,%4%p1"
