https://gcc.gnu.org/g:b76d14f773375487e534233fa2b3a5bcdb81da11
commit r17-5751-gb76d14f773375487e534233fa2b3a5bcdb81da11 Author: Pan Li <[email protected]> Date: Thu Oct 29 10:16:53 2026 +0800 RISC-V: Add test cases to ensure no reg overlap for vwabdau.vv [PR target/128162] Add test cases for the register group overlap of the widening absolute difference and accumulate insn vwabdau.vv, to ensure the vs1 and vs2 will not fall inside the vd register group. PR target/128162 gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/group_overlap/vwabdau_vv-u8-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwabdau_vv-u8-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwabdau_vv-u8-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwabdau_vv-u16-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwabdau_vv-u16-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwabdau_vv-u16-m4.c: New test. * gcc.target/riscv/rvv/base/pr128162-2.c: New test. Signed-off-by: Pan Li <[email protected]> Diff: --- .../rvv/autovec/group_overlap/vwabdau_vv-u16-m1.c | 28 ++++++ .../rvv/autovec/group_overlap/vwabdau_vv-u16-m2.c | 28 ++++++ .../rvv/autovec/group_overlap/vwabdau_vv-u16-m4.c | 28 ++++++ .../rvv/autovec/group_overlap/vwabdau_vv-u8-m1.c | 28 ++++++ .../rvv/autovec/group_overlap/vwabdau_vv-u8-m2.c | 28 ++++++ .../rvv/autovec/group_overlap/vwabdau_vv-u8-m4.c | 28 ++++++ .../gcc.target/riscv/rvv/base/pr128162-2.c | 109 +++++++++++++++++++++ 7 files changed, 277 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabdau_vv-u16-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabdau_vv-u16-m1.c new file mode 100644 index 000000000000..2a2c9cb5b663 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabdau_vv-u16-m1.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvabd -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_TERNARY_0( + __riscv_vsetvlmax_e16m1, + vuint16m1_t, + vuint32m2_t, + vuint16m2_t, + __riscv_vle16_v_u16m1, + __riscv_vle32_v_u32m2, + __riscv_vreinterpret_v_u32m2_u16m2, + __riscv_vget_v_u16m2_u16m1, + 1, + __riscv_vwabdau_vv_u32m2, + __riscv_vse32_v_u32m2, + vwabdau_vv, + LOOP_WIDEN_TERNARY_BODY_OVERLAP_X2) + +/* { dg-final { scan-assembler-times {vwabdau\.vv\s+v6,v5,v8([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwabdau\.vv\s+v4,v1,v3([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v6,v(6|7),} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v6,v[0-9]+,v(6|7)([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v4,v(4|5),} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v4,v[0-9]+,v(4|5)([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v2,v(2|3),} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v2,v[0-9]+,v(2|3)([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabdau_vv-u16-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabdau_vv-u16-m2.c new file mode 100644 index 000000000000..ba5aa5079ebf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabdau_vv-u16-m2.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvabd -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_TERNARY_0( + __riscv_vsetvlmax_e16m2, + vuint16m2_t, + vuint32m4_t, + vuint16m4_t, + __riscv_vle16_v_u16m2, + __riscv_vle32_v_u32m4, + __riscv_vreinterpret_v_u32m4_u16m4, + __riscv_vget_v_u16m4_u16m2, + 1, + __riscv_vwabdau_vv_u32m4, + __riscv_vse32_v_u32m4, + vwabdau_vv, + LOOP_WIDEN_TERNARY_BODY_OVERLAP_X2) + +/* { dg-final { scan-assembler-times {vwabdau\.vv\s+v12,v10,v16([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwabdau\.vv\s+v8,v2,v6([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v12,v(12|13|14|15),} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v12,v[0-9]+,v(12|13|14|15)([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v8,v(8|9|10|11),} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v8,v[0-9]+,v(8|9|10|11)([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v4,v(4|5|6|7),} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v4,v[0-9]+,v(4|5|6|7)([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabdau_vv-u16-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabdau_vv-u16-m4.c new file mode 100644 index 000000000000..c1967e3b6d57 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabdau_vv-u16-m4.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvabd -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_TERNARY_0( + __riscv_vsetvlmax_e16m4, + vuint16m4_t, + vuint32m8_t, + vuint16m8_t, + __riscv_vle16_v_u16m4, + __riscv_vle32_v_u32m8, + __riscv_vreinterpret_v_u32m8_u16m8, + __riscv_vget_v_u16m8_u16m4, + 1, + __riscv_vwabdau_vv_u32m8, + __riscv_vse32_v_u32m8, + vwabdau_vv, + LOOP_WIDEN_TERNARY_BODY_OVERLAP_X2) + +/* { dg-final { scan-assembler-times {vwabdau\.vv\s+v24,v20,v0([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwabdau\.vv\s+v16,v4,v12([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v24,v(24|25|26|27|28|29|30|31),} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v24,v[0-9]+,v(24|25|26|27|28|29|30|31)([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v16,v(16|17|18|19|20|21|22|23),} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v16,v[0-9]+,v(16|17|18|19|20|21|22|23)([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v8,v(8|9|10|11|12|13|14|15),} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v8,v[0-9]+,v(8|9|10|11|12|13|14|15)([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabdau_vv-u8-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabdau_vv-u8-m1.c new file mode 100644 index 000000000000..11199b096097 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabdau_vv-u8-m1.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvabd -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_TERNARY_0( + __riscv_vsetvlmax_e8m1, + vuint8m1_t, + vuint16m2_t, + vuint8m2_t, + __riscv_vle8_v_u8m1, + __riscv_vle16_v_u16m2, + __riscv_vreinterpret_v_u16m2_u8m2, + __riscv_vget_v_u8m2_u8m1, + 1, + __riscv_vwabdau_vv_u16m2, + __riscv_vse16_v_u16m2, + vwabdau_vv, + LOOP_WIDEN_TERNARY_BODY_OVERLAP_X2) + +/* { dg-final { scan-assembler-times {vwabdau\.vv\s+v6,v5,v8([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwabdau\.vv\s+v4,v1,v3([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v6,v(6|7),} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v6,v[0-9]+,v(6|7)([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v4,v(4|5),} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v4,v[0-9]+,v(4|5)([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v2,v(2|3),} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v2,v[0-9]+,v(2|3)([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabdau_vv-u8-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabdau_vv-u8-m2.c new file mode 100644 index 000000000000..d09d212c0f53 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabdau_vv-u8-m2.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvabd -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_TERNARY_0( + __riscv_vsetvlmax_e8m2, + vuint8m2_t, + vuint16m4_t, + vuint8m4_t, + __riscv_vle8_v_u8m2, + __riscv_vle16_v_u16m4, + __riscv_vreinterpret_v_u16m4_u8m4, + __riscv_vget_v_u8m4_u8m2, + 1, + __riscv_vwabdau_vv_u16m4, + __riscv_vse16_v_u16m4, + vwabdau_vv, + LOOP_WIDEN_TERNARY_BODY_OVERLAP_X2) + +/* { dg-final { scan-assembler-times {vwabdau\.vv\s+v12,v10,v16([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwabdau\.vv\s+v8,v2,v6([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v12,v(12|13|14|15),} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v12,v[0-9]+,v(12|13|14|15)([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v8,v(8|9|10|11),} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v8,v[0-9]+,v(8|9|10|11)([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v4,v(4|5|6|7),} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v4,v[0-9]+,v(4|5|6|7)([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabdau_vv-u8-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabdau_vv-u8-m4.c new file mode 100644 index 000000000000..0d8fa2da971f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabdau_vv-u8-m4.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvabd -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_TERNARY_0( + __riscv_vsetvlmax_e8m4, + vuint8m4_t, + vuint16m8_t, + vuint8m8_t, + __riscv_vle8_v_u8m4, + __riscv_vle16_v_u16m8, + __riscv_vreinterpret_v_u16m8_u8m8, + __riscv_vget_v_u8m8_u8m4, + 1, + __riscv_vwabdau_vv_u16m8, + __riscv_vse16_v_u16m8, + vwabdau_vv, + LOOP_WIDEN_TERNARY_BODY_OVERLAP_X2) + +/* { dg-final { scan-assembler-times {vwabdau\.vv\s+v24,v20,v0([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwabdau\.vv\s+v16,v4,v12([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v24,v(24|25|26|27|28|29|30|31),} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v24,v[0-9]+,v(24|25|26|27|28|29|30|31)([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v16,v(16|17|18|19|20|21|22|23),} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v16,v[0-9]+,v(16|17|18|19|20|21|22|23)([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v8,v(8|9|10|11|12|13|14|15),} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v8,v[0-9]+,v(8|9|10|11|12|13|14|15)([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr128162-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr128162-2.c new file mode 100644 index 000000000000..465bd3c2f3ca --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr128162-2.c @@ -0,0 +1,109 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvabd -mabi=lp64d -O2" } */ +/* PR target/128162 */ + +#include "riscv_vector.h" + +vuint32m2_t +test_vwabdau_vs2_u32m2 (vuint32m2_t vd, vuint16m1_t vs, size_t vl) +{ + vuint16m2_t t = __riscv_vreinterpret_v_u32m2_u16m2 (vd); + vuint16m1_t hi = __riscv_vget_v_u16m2_u16m1 (t, 1); + return __riscv_vwabdau_vv_u32m2 (vd, hi, vs, vl); +} + +vuint32m2_t +test_vwabdau_vs1_u32m2 (vuint32m2_t vd, vuint16m1_t vs, size_t vl) +{ + vuint16m2_t t = __riscv_vreinterpret_v_u32m2_u16m2 (vd); + vuint16m1_t hi = __riscv_vget_v_u16m2_u16m1 (t, 1); + return __riscv_vwabdau_vv_u32m2 (vd, vs, hi, vl); +} + +vuint32m4_t +test_vwabdau_vs2_u32m4 (vuint32m4_t vd, vuint16m2_t vs, size_t vl) +{ + vuint16m4_t t = __riscv_vreinterpret_v_u32m4_u16m4 (vd); + vuint16m2_t hi = __riscv_vget_v_u16m4_u16m2 (t, 1); + return __riscv_vwabdau_vv_u32m4 (vd, hi, vs, vl); +} + +vuint32m4_t +test_vwabdau_vs1_u32m4 (vuint32m4_t vd, vuint16m2_t vs, size_t vl) +{ + vuint16m4_t t = __riscv_vreinterpret_v_u32m4_u16m4 (vd); + vuint16m2_t hi = __riscv_vget_v_u16m4_u16m2 (t, 1); + return __riscv_vwabdau_vv_u32m4 (vd, vs, hi, vl); +} + +vuint32m8_t +test_vwabdau_vs2_u32m8 (vuint32m8_t vd, vuint16m4_t vs, size_t vl) +{ + vuint16m8_t t = __riscv_vreinterpret_v_u32m8_u16m8 (vd); + vuint16m4_t hi = __riscv_vget_v_u16m8_u16m4 (t, 1); + return __riscv_vwabdau_vv_u32m8 (vd, hi, vs, vl); +} + +vuint32m8_t +test_vwabdau_vs1_u32m8 (vuint32m8_t vd, vuint16m4_t vs, size_t vl) +{ + vuint16m8_t t = __riscv_vreinterpret_v_u32m8_u16m8 (vd); + vuint16m4_t hi = __riscv_vget_v_u16m8_u16m4 (t, 1); + return __riscv_vwabdau_vv_u32m8 (vd, vs, hi, vl); +} + +vuint16m2_t +test_vwabdau_vs2_u16m2 (vuint16m2_t vd, vuint8m1_t vs, size_t vl) +{ + vuint8m2_t t = __riscv_vreinterpret_v_u16m2_u8m2 (vd); + vuint8m1_t hi = __riscv_vget_v_u8m2_u8m1 (t, 1); + return __riscv_vwabdau_vv_u16m2 (vd, hi, vs, vl); +} + +vuint16m2_t +test_vwabdau_vs1_u16m2 (vuint16m2_t vd, vuint8m1_t vs, size_t vl) +{ + vuint8m2_t t = __riscv_vreinterpret_v_u16m2_u8m2 (vd); + vuint8m1_t hi = __riscv_vget_v_u8m2_u8m1 (t, 1); + return __riscv_vwabdau_vv_u16m2 (vd, vs, hi, vl); +} + +vuint16m4_t +test_vwabdau_vs2_u16m4 (vuint16m4_t vd, vuint8m2_t vs, size_t vl) +{ + vuint8m4_t t = __riscv_vreinterpret_v_u16m4_u8m4 (vd); + vuint8m2_t hi = __riscv_vget_v_u8m4_u8m2 (t, 1); + return __riscv_vwabdau_vv_u16m4 (vd, hi, vs, vl); +} + +vuint16m4_t +test_vwabdau_vs1_u16m4 (vuint16m4_t vd, vuint8m2_t vs, size_t vl) +{ + vuint8m4_t t = __riscv_vreinterpret_v_u16m4_u8m4 (vd); + vuint8m2_t hi = __riscv_vget_v_u8m4_u8m2 (t, 1); + return __riscv_vwabdau_vv_u16m4 (vd, vs, hi, vl); +} + +vuint16m8_t +test_vwabdau_vs2_u16m8 (vuint16m8_t vd, vuint8m4_t vs, size_t vl) +{ + vuint8m8_t t = __riscv_vreinterpret_v_u16m8_u8m8 (vd); + vuint8m4_t hi = __riscv_vget_v_u8m8_u8m4 (t, 1); + return __riscv_vwabdau_vv_u16m8 (vd, hi, vs, vl); +} + +vuint16m8_t +test_vwabdau_vs1_u16m8 (vuint16m8_t vd, vuint8m4_t vs, size_t vl) +{ + vuint8m8_t t = __riscv_vreinterpret_v_u16m8_u8m8 (vd); + vuint8m4_t hi = __riscv_vget_v_u8m8_u8m4 (t, 1); + return __riscv_vwabdau_vv_u16m8 (vd, vs, hi, vl); +} + +/* { dg-final { scan-assembler-times {vwabdau\.vv\s+} 12 } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v8,v9,} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v8,v[0-9]+,v9([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v8,v10,} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v8,v[0-9]+,v10([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v8,v12,} } } */ +/* { dg-final { scan-assembler-not {vwabdau\.vv\s+v8,v[0-9]+,v12([^0-9]|$)} } } */
