https://gcc.gnu.org/g:b71062341c90ce952e0a07103d6aed9a5c5917d6
commit r17-5750-gb71062341c90ce952e0a07103d6aed9a5c5917d6 Author: Pan Li <[email protected]> Date: Thu Oct 29 10:16:53 2026 +0800 RISC-V: Add test cases to ensure no reg overlap for vwabda.vv [PR target/128162] Add test cases for the register group overlap of the widening absolute difference and accumulate insn vwabda.vv, to ensure the vs1 and vs2 will not fall inside the vd register group. PR target/128162 gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/group_overlap/group_overlap.h: Add test helper macros. * gcc.target/riscv/rvv/autovec/group_overlap/vwabda_vv-i8-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwabda_vv-i8-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwabda_vv-i8-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwabda_vv-i16-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwabda_vv-i16-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwabda_vv-i16-m4.c: New test. * gcc.target/riscv/rvv/base/pr128162-1.c: New test. Signed-off-by: Pan Li <[email protected]> Diff: --- .../rvv/autovec/group_overlap/group_overlap.h | 47 ++++++++ .../rvv/autovec/group_overlap/vwabda_vv-i16-m1.c | 31 ++++++ .../rvv/autovec/group_overlap/vwabda_vv-i16-m2.c | 31 ++++++ .../rvv/autovec/group_overlap/vwabda_vv-i16-m4.c | 31 ++++++ .../rvv/autovec/group_overlap/vwabda_vv-i8-m1.c | 31 ++++++ .../rvv/autovec/group_overlap/vwabda_vv-i8-m2.c | 31 ++++++ .../rvv/autovec/group_overlap/vwabda_vv-i8-m4.c | 31 ++++++ .../gcc.target/riscv/rvv/base/pr128162-1.c | 121 +++++++++++++++++++++ 8 files changed, 354 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/group_overlap.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/group_overlap.h index 45f8f45e85b3..5e1c8f017ef1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/group_overlap.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/group_overlap.h @@ -692,6 +692,36 @@ ST_F ((void *)out, vd0, VL); OUT += VL; \ ST_F ((void *)out, vd1, VL); OUT += VL; \ +/* A widening accumulate like vwabda.vv reads vd with EEW = 2 * SEW while vs2 + and vs1 are read with EEW = SEW, thus neither vs2 nor vs1 may fall inside + the vd register group. RI_F reinterprets the widened accumulator as the + narrowed element type and GET_F extracts its IDX-th piece, which lives in + the vd register group. Then take that piece as vs2 for vd0 and as vs1 for + vd1 to ask for the overlap. */ +#define LOOP_WIDEN_TERNARY_BODY_OVERLAP_X2(NT, WT, WNT, LD_NF, LD_WF, RI_F, \ + GET_F, IDX, OUT_F, ST_F, OUT, \ + START, VL) \ + WT vw0 = LD_WF ((void *)START, VL); START += VL; \ + WT vw1 = LD_WF ((void *)START, VL); START += VL; \ + NT vs0 = LD_NF ((void *)START, VL); START += VL; \ + NT vs1 = LD_NF ((void *)START, VL); START += VL; \ + \ + asm volatile("nop" ::: "memory"); \ + \ + WNT vr0 = RI_F (vw0); \ + WNT vr1 = RI_F (vw1); \ + \ + NT vt0 = GET_F (vr0, IDX); \ + NT vt1 = GET_F (vr1, IDX); \ + \ + WT vd0 = OUT_F (vw0, vt0, vs0, VL); \ + WT vd1 = OUT_F (vw1, vs1, vt1, VL); \ + \ + asm volatile("nop" ::: "memory"); \ + \ + ST_F ((void *)out, vd0, VL); OUT += VL; \ + ST_F ((void *)out, vd1, VL); OUT += VL; \ + #define DEF_GROUP_OVERLAP_UNARY_0(VL_F, NT, WT, LD_F, OUT_F, ST_F, NAME, \ LOOP_BODY) \ void test_group_overlap_##NAME##_##NT##_unary_0(uint8_t *data, \ @@ -800,4 +830,21 @@ } \ } +#define DEF_GROUP_OVERLAP_TERNARY_0(VL_F, NT, WT, WNT, LD_NF, LD_WF, RI_F, \ + GET_F, IDX, OUT_F, ST_F, NAME, \ + LOOP_BODY) \ + void test_group_overlap_##NAME##_##NT##_ternary_0(uint8_t *data, \ + uint8_t *out, \ + size_t limit) \ + { \ + uint8_t *start = data; \ + uint8_t *end = data + limit; \ + size_t vl = VL_F (); \ + \ + while (start < end) { \ + LOOP_BODY (NT, WT, WNT, LD_NF, LD_WF, RI_F, GET_F, IDX, OUT_F, ST_F, \ + out, start, vl); \ + } \ + } + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabda_vv-i16-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabda_vv-i16-m1.c new file mode 100644 index 000000000000..af22db541e7f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabda_vv-i16-m1.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvabd -mabi=lp64d" } */ + +#include "group_overlap.h" + +#define RI_F(v) \ + __riscv_vreinterpret_v_i32m2_i16m2 (__riscv_vreinterpret_v_u32m2_i32m2 (v)) + +DEF_GROUP_OVERLAP_TERNARY_0( + __riscv_vsetvlmax_e16m1, + vint16m1_t, + vuint32m2_t, + vint16m2_t, + __riscv_vle16_v_i16m1, + __riscv_vle32_v_u32m2, + RI_F, + __riscv_vget_v_i16m2_i16m1, + 1, + __riscv_vwabda_vv_u32m2, + __riscv_vse32_v_u32m2, + vwabda_vv, + LOOP_WIDEN_TERNARY_BODY_OVERLAP_X2) + +/* { dg-final { scan-assembler-times {vwabda\.vv\s+v6,v5,v8([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwabda\.vv\s+v4,v1,v3([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v6,v(6|7),} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v6,v[0-9]+,v(6|7)([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v4,v(4|5),} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v4,v[0-9]+,v(4|5)([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v2,v(2|3),} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v2,v[0-9]+,v(2|3)([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabda_vv-i16-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabda_vv-i16-m2.c new file mode 100644 index 000000000000..48ce54c9d45e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabda_vv-i16-m2.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvabd -mabi=lp64d" } */ + +#include "group_overlap.h" + +#define RI_F(v) \ + __riscv_vreinterpret_v_i32m4_i16m4 (__riscv_vreinterpret_v_u32m4_i32m4 (v)) + +DEF_GROUP_OVERLAP_TERNARY_0( + __riscv_vsetvlmax_e16m2, + vint16m2_t, + vuint32m4_t, + vint16m4_t, + __riscv_vle16_v_i16m2, + __riscv_vle32_v_u32m4, + RI_F, + __riscv_vget_v_i16m4_i16m2, + 1, + __riscv_vwabda_vv_u32m4, + __riscv_vse32_v_u32m4, + vwabda_vv, + LOOP_WIDEN_TERNARY_BODY_OVERLAP_X2) + +/* { dg-final { scan-assembler-times {vwabda\.vv\s+v12,v10,v16([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwabda\.vv\s+v8,v2,v6([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v12,v(12|13|14|15),} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v12,v[0-9]+,v(12|13|14|15)([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v8,v(8|9|10|11),} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v8,v[0-9]+,v(8|9|10|11)([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v4,v(4|5|6|7),} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v4,v[0-9]+,v(4|5|6|7)([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabda_vv-i16-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabda_vv-i16-m4.c new file mode 100644 index 000000000000..9e056f782915 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabda_vv-i16-m4.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvabd -mabi=lp64d" } */ + +#include "group_overlap.h" + +#define RI_F(v) \ + __riscv_vreinterpret_v_i32m8_i16m8 (__riscv_vreinterpret_v_u32m8_i32m8 (v)) + +DEF_GROUP_OVERLAP_TERNARY_0( + __riscv_vsetvlmax_e16m4, + vint16m4_t, + vuint32m8_t, + vint16m8_t, + __riscv_vle16_v_i16m4, + __riscv_vle32_v_u32m8, + RI_F, + __riscv_vget_v_i16m8_i16m4, + 1, + __riscv_vwabda_vv_u32m8, + __riscv_vse32_v_u32m8, + vwabda_vv, + LOOP_WIDEN_TERNARY_BODY_OVERLAP_X2) + +/* { dg-final { scan-assembler-times {vwabda\.vv\s+v24,v20,v0([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwabda\.vv\s+v16,v4,v12([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v24,v(24|25|26|27|28|29|30|31),} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v24,v[0-9]+,v(24|25|26|27|28|29|30|31)([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v16,v(16|17|18|19|20|21|22|23),} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v16,v[0-9]+,v(16|17|18|19|20|21|22|23)([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v8,v(8|9|10|11|12|13|14|15),} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v8,v[0-9]+,v(8|9|10|11|12|13|14|15)([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabda_vv-i8-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabda_vv-i8-m1.c new file mode 100644 index 000000000000..4e0248ca79d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabda_vv-i8-m1.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvabd -mabi=lp64d" } */ + +#include "group_overlap.h" + +#define RI_F(v) \ + __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vreinterpret_v_u16m2_i16m2 (v)) + +DEF_GROUP_OVERLAP_TERNARY_0( + __riscv_vsetvlmax_e8m1, + vint8m1_t, + vuint16m2_t, + vint8m2_t, + __riscv_vle8_v_i8m1, + __riscv_vle16_v_u16m2, + RI_F, + __riscv_vget_v_i8m2_i8m1, + 1, + __riscv_vwabda_vv_u16m2, + __riscv_vse16_v_u16m2, + vwabda_vv, + LOOP_WIDEN_TERNARY_BODY_OVERLAP_X2) + +/* { dg-final { scan-assembler-times {vwabda\.vv\s+v6,v5,v8([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwabda\.vv\s+v4,v1,v3([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v6,v(6|7),} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v6,v[0-9]+,v(6|7)([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v4,v(4|5),} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v4,v[0-9]+,v(4|5)([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v2,v(2|3),} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v2,v[0-9]+,v(2|3)([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabda_vv-i8-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabda_vv-i8-m2.c new file mode 100644 index 000000000000..e15bb27f0519 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabda_vv-i8-m2.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvabd -mabi=lp64d" } */ + +#include "group_overlap.h" + +#define RI_F(v) \ + __riscv_vreinterpret_v_i16m4_i8m4 (__riscv_vreinterpret_v_u16m4_i16m4 (v)) + +DEF_GROUP_OVERLAP_TERNARY_0( + __riscv_vsetvlmax_e8m2, + vint8m2_t, + vuint16m4_t, + vint8m4_t, + __riscv_vle8_v_i8m2, + __riscv_vle16_v_u16m4, + RI_F, + __riscv_vget_v_i8m4_i8m2, + 1, + __riscv_vwabda_vv_u16m4, + __riscv_vse16_v_u16m4, + vwabda_vv, + LOOP_WIDEN_TERNARY_BODY_OVERLAP_X2) + +/* { dg-final { scan-assembler-times {vwabda\.vv\s+v12,v10,v16([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwabda\.vv\s+v8,v2,v6([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v12,v(12|13|14|15),} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v12,v[0-9]+,v(12|13|14|15)([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v8,v(8|9|10|11),} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v8,v[0-9]+,v(8|9|10|11)([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v4,v(4|5|6|7),} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v4,v[0-9]+,v(4|5|6|7)([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabda_vv-i8-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabda_vv-i8-m4.c new file mode 100644 index 000000000000..c9a64a1a74ba --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwabda_vv-i8-m4.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvabd -mabi=lp64d" } */ + +#include "group_overlap.h" + +#define RI_F(v) \ + __riscv_vreinterpret_v_i16m8_i8m8 (__riscv_vreinterpret_v_u16m8_i16m8 (v)) + +DEF_GROUP_OVERLAP_TERNARY_0( + __riscv_vsetvlmax_e8m4, + vint8m4_t, + vuint16m8_t, + vint8m8_t, + __riscv_vle8_v_i8m4, + __riscv_vle16_v_u16m8, + RI_F, + __riscv_vget_v_i8m8_i8m4, + 1, + __riscv_vwabda_vv_u16m8, + __riscv_vse16_v_u16m8, + vwabda_vv, + LOOP_WIDEN_TERNARY_BODY_OVERLAP_X2) + +/* { dg-final { scan-assembler-times {vwabda\.vv\s+v24,v20,v0([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwabda\.vv\s+v16,v4,v12([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v24,v(24|25|26|27|28|29|30|31),} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v24,v[0-9]+,v(24|25|26|27|28|29|30|31)([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v16,v(16|17|18|19|20|21|22|23),} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v16,v[0-9]+,v(16|17|18|19|20|21|22|23)([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v8,v(8|9|10|11|12|13|14|15),} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v8,v[0-9]+,v(8|9|10|11|12|13|14|15)([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr128162-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr128162-1.c new file mode 100644 index 000000000000..32906fed1a50 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr128162-1.c @@ -0,0 +1,121 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvabd -mabi=lp64d -O2" } */ +/* PR target/128162 */ + +#include "riscv_vector.h" + +vuint32m2_t +test_vwabda_vs2_u32m2 (vuint32m2_t vd, vint16m1_t vs, size_t vl) +{ + vint32m2_t s = __riscv_vreinterpret_v_u32m2_i32m2 (vd); + vint16m2_t t = __riscv_vreinterpret_v_i32m2_i16m2 (s); + vint16m1_t hi = __riscv_vget_v_i16m2_i16m1 (t, 1); + return __riscv_vwabda_vv_u32m2 (vd, hi, vs, vl); +} + +vuint32m2_t +test_vwabda_vs1_u32m2 (vuint32m2_t vd, vint16m1_t vs, size_t vl) +{ + vint32m2_t s = __riscv_vreinterpret_v_u32m2_i32m2 (vd); + vint16m2_t t = __riscv_vreinterpret_v_i32m2_i16m2 (s); + vint16m1_t hi = __riscv_vget_v_i16m2_i16m1 (t, 1); + return __riscv_vwabda_vv_u32m2 (vd, vs, hi, vl); +} + +vuint32m4_t +test_vwabda_vs2_u32m4 (vuint32m4_t vd, vint16m2_t vs, size_t vl) +{ + vint32m4_t s = __riscv_vreinterpret_v_u32m4_i32m4 (vd); + vint16m4_t t = __riscv_vreinterpret_v_i32m4_i16m4 (s); + vint16m2_t hi = __riscv_vget_v_i16m4_i16m2 (t, 1); + return __riscv_vwabda_vv_u32m4 (vd, hi, vs, vl); +} + +vuint32m4_t +test_vwabda_vs1_u32m4 (vuint32m4_t vd, vint16m2_t vs, size_t vl) +{ + vint32m4_t s = __riscv_vreinterpret_v_u32m4_i32m4 (vd); + vint16m4_t t = __riscv_vreinterpret_v_i32m4_i16m4 (s); + vint16m2_t hi = __riscv_vget_v_i16m4_i16m2 (t, 1); + return __riscv_vwabda_vv_u32m4 (vd, vs, hi, vl); +} + +vuint32m8_t +test_vwabda_vs2_u32m8 (vuint32m8_t vd, vint16m4_t vs, size_t vl) +{ + vint32m8_t s = __riscv_vreinterpret_v_u32m8_i32m8 (vd); + vint16m8_t t = __riscv_vreinterpret_v_i32m8_i16m8 (s); + vint16m4_t hi = __riscv_vget_v_i16m8_i16m4 (t, 1); + return __riscv_vwabda_vv_u32m8 (vd, hi, vs, vl); +} + +vuint32m8_t +test_vwabda_vs1_u32m8 (vuint32m8_t vd, vint16m4_t vs, size_t vl) +{ + vint32m8_t s = __riscv_vreinterpret_v_u32m8_i32m8 (vd); + vint16m8_t t = __riscv_vreinterpret_v_i32m8_i16m8 (s); + vint16m4_t hi = __riscv_vget_v_i16m8_i16m4 (t, 1); + return __riscv_vwabda_vv_u32m8 (vd, vs, hi, vl); +} + +vuint16m2_t +test_vwabda_vs2_u16m2 (vuint16m2_t vd, vint8m1_t vs, size_t vl) +{ + vint16m2_t s = __riscv_vreinterpret_v_u16m2_i16m2 (vd); + vint8m2_t t = __riscv_vreinterpret_v_i16m2_i8m2 (s); + vint8m1_t hi = __riscv_vget_v_i8m2_i8m1 (t, 1); + return __riscv_vwabda_vv_u16m2 (vd, hi, vs, vl); +} + +vuint16m2_t +test_vwabda_vs1_u16m2 (vuint16m2_t vd, vint8m1_t vs, size_t vl) +{ + vint16m2_t s = __riscv_vreinterpret_v_u16m2_i16m2 (vd); + vint8m2_t t = __riscv_vreinterpret_v_i16m2_i8m2 (s); + vint8m1_t hi = __riscv_vget_v_i8m2_i8m1 (t, 1); + return __riscv_vwabda_vv_u16m2 (vd, vs, hi, vl); +} + +vuint16m4_t +test_vwabda_vs2_u16m4 (vuint16m4_t vd, vint8m2_t vs, size_t vl) +{ + vint16m4_t s = __riscv_vreinterpret_v_u16m4_i16m4 (vd); + vint8m4_t t = __riscv_vreinterpret_v_i16m4_i8m4 (s); + vint8m2_t hi = __riscv_vget_v_i8m4_i8m2 (t, 1); + return __riscv_vwabda_vv_u16m4 (vd, hi, vs, vl); +} + +vuint16m4_t +test_vwabda_vs1_u16m4 (vuint16m4_t vd, vint8m2_t vs, size_t vl) +{ + vint16m4_t s = __riscv_vreinterpret_v_u16m4_i16m4 (vd); + vint8m4_t t = __riscv_vreinterpret_v_i16m4_i8m4 (s); + vint8m2_t hi = __riscv_vget_v_i8m4_i8m2 (t, 1); + return __riscv_vwabda_vv_u16m4 (vd, vs, hi, vl); +} + +vuint16m8_t +test_vwabda_vs2_u16m8 (vuint16m8_t vd, vint8m4_t vs, size_t vl) +{ + vint16m8_t s = __riscv_vreinterpret_v_u16m8_i16m8 (vd); + vint8m8_t t = __riscv_vreinterpret_v_i16m8_i8m8 (s); + vint8m4_t hi = __riscv_vget_v_i8m8_i8m4 (t, 1); + return __riscv_vwabda_vv_u16m8 (vd, hi, vs, vl); +} + +vuint16m8_t +test_vwabda_vs1_u16m8 (vuint16m8_t vd, vint8m4_t vs, size_t vl) +{ + vint16m8_t s = __riscv_vreinterpret_v_u16m8_i16m8 (vd); + vint8m8_t t = __riscv_vreinterpret_v_i16m8_i8m8 (s); + vint8m4_t hi = __riscv_vget_v_i8m8_i8m4 (t, 1); + return __riscv_vwabda_vv_u16m8 (vd, vs, hi, vl); +} + +/* { dg-final { scan-assembler-times {vwabda\.vv\s+} 12 } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v8,v9,} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v8,v[0-9]+,v9([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v8,v10,} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v8,v[0-9]+,v10([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v8,v12,} } } */ +/* { dg-final { scan-assembler-not {vwabda\.vv\s+v8,v[0-9]+,v12([^0-9]|$)} } } */
