From: Lino Hsing-Yu Peng <[email protected]> This series adds initial GCC support for the RISC-V Zvfofp8min extension.
It first introduces Zvfofp8min ISA extension support, then adds FP8 conversion support in RVV builtins and machine descriptions (FP8<->BF16 and FP32->FP8), and updates vsetvl handling so altfmt requirements are propagated from instruction patterns through vsetvl generation and the vsetvl pass. The final patch adds testsuite coverage under gcc.target/riscv/rvv, including policy/non-policy and overloaded/non-overloaded variants for vfncvt, vfncvtbf16, and vfwcvtbf16, plus an altfmt interleave test. Lino Hsing-Yu Peng (8): RISC-V: Add zvfofp8min ISA extension support RISC-V: Add zvfofp8min FP8 to BF16 vector conversions RISC-V: Add zvfofp8min BF16 to FP8 narrowing conversions RISC-V: Add zvfofp8min FP32 to FP8 narrowing conversions RISC-V: Plumb altfmt through vsetvl patterns RISC-V: Mark zvfofp8min altfmt on insns RISC-V: Track altfmt in vsetvl pass RISC-V: Add zvfofp8min tests gcc/common/config/riscv/riscv-common.cc | 2 + gcc/config/riscv/genrvv-type-indexer.cc | 10 + gcc/config/riscv/riscv-ext.def | 13 + gcc/config/riscv/riscv-ext.opt | 3 +- gcc/config/riscv/riscv-v.cc | 8 +- .../riscv/riscv-vector-builtins-bases.cc | 118 ++- .../riscv/riscv-vector-builtins-bases.h | 3 + .../riscv/riscv-vector-builtins-functions.def | 23 + .../riscv/riscv-vector-builtins-shapes.cc | 191 ++++- .../riscv/riscv-vector-builtins-shapes.h | 7 + .../riscv/riscv-vector-builtins-types.def | 14 + gcc/config/riscv/riscv-vector-builtins.cc | 63 +- gcc/config/riscv/riscv-vector-builtins.def | 8 +- gcc/config/riscv/riscv-vector-builtins.h | 7 + gcc/config/riscv/riscv-vsetvl.cc | 189 ++++- gcc/config/riscv/riscv-vsetvl.def | 15 + gcc/config/riscv/riscv.md | 6 + gcc/config/riscv/vector-float8.md | 154 ++++ gcc/config/riscv/vector.md | 74 +- gcc/doc/riscv-ext.texi | 4 + gcc/testsuite/gcc.target/riscv/arch-61.c | 5 + .../rvv/base/zvfofp8min-altfmt-interleave.c | 59 ++ gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 3 + .../non-policy/non-overloaded/riscv_vector.h | 11 + .../non-policy/non-overloaded/vfncvt.c | 326 ++++++++ .../non-policy/non-overloaded/vfncvtbf16.c | 390 +++++++++ .../non-policy/non-overloaded/vfwcvtbf16.c | 102 +++ .../non-policy/overloaded/riscv_vector.h | 11 + .../zvfofp8min/non-policy/overloaded/vfncvt.c | 326 ++++++++ .../non-policy/overloaded/vfncvtbf16.c | 390 +++++++++ .../non-policy/overloaded/vfwcvtbf16.c | 102 +++ .../policy/non-overloaded/riscv_vector.h | 11 + .../zvfofp8min/policy/non-overloaded/vfncvt.c | 646 +++++++++++++++ .../policy/non-overloaded/vfncvtbf16.c | 774 ++++++++++++++++++ .../policy/non-overloaded/vfwcvtbf16.c | 198 +++++ .../policy/overloaded/riscv_vector.h | 11 + .../rvv/zvfofp8min/policy/overloaded/vfncvt.c | 646 +++++++++++++++ .../zvfofp8min/policy/overloaded/vfncvtbf16.c | 774 ++++++++++++++++++ .../zvfofp8min/policy/overloaded/vfwcvtbf16.c | 198 +++++ 39 files changed, 5818 insertions(+), 77 deletions(-) create mode 100644 gcc/config/riscv/vector-float8.md create mode 100644 gcc/testsuite/gcc.target/riscv/arch-61.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfofp8min-altfmt-interleave.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/non-policy/non-overloaded/riscv_vector.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/non-policy/non-overloaded/vfncvt.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/non-policy/overloaded/riscv_vector.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/non-policy/overloaded/vfncvt.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/non-policy/overloaded/vfncvtbf16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/policy/non-overloaded/riscv_vector.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/policy/non-overloaded/vfncvt.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/policy/non-overloaded/vfncvtbf16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/policy/overloaded/riscv_vector.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/policy/overloaded/vfncvt.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/policy/overloaded/vfncvtbf16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/policy/overloaded/vfwcvtbf16.c -- 2.34.1
