From: Lino Hsing-Yu Peng <[email protected]>
Thread an explicit altfmt attribute through vsetvl patterns and their
callers so vsetvl emission can request e<sew>alt encoding when needed.
Keep ALTFMT_NONE as the default for existing expansion paths.
gcc/ChangeLog:
* config/riscv/vector.md (altfmt): New attribute.
(@vsetvl<mode>, vsetvl_vtype_change_only): Add altfmt operand and
emit e%sewalt when requested.
(@vsetvl_discard_result<mode>, @vsetvl<mode>_volatile): Likewise.
(@vsetvl<mode>_no_side_effects, *vsetvldi_no_side_effects_si_extend):
Carry altfmt through attributes.
* config/riscv/riscv-v.cc (emit_hard_vlmax_vsetvl,
gen_no_side_effects_vsetvl_rtx): Pass ALTFMT_NONE.
* config/riscv/riscv-vsetvl.cc (get_vsetvl_pat): Pass default altfmt.
* config/riscv/riscv-vector-builtins-bases.cc: Include insn-attr.h.
(vsetvl::expand): Add ALTFMT_NONE operand.
---
gcc/config/riscv/riscv-v.cc | 8 +-
.../riscv/riscv-vector-builtins-bases.cc | 4 +
gcc/config/riscv/riscv-vsetvl.cc | 8 +-
gcc/config/riscv/vector.md | 74 +++++++++++++------
4 files changed, 66 insertions(+), 28 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 29dc3ebccd6..ac102498ad3 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -866,9 +866,10 @@ void
emit_hard_vlmax_vsetvl (machine_mode vmode, rtx vl)
{
unsigned int sew = get_sew (vmode);
+ rtx altfmt = gen_int_mode (ALTFMT_NONE, Pmode);
emit_insn (gen_vsetvl (Pmode, vl, RVV_VLMAX, gen_int_mode (sew, Pmode),
- gen_int_mode (get_vlmul (vmode), Pmode), const0_rtx,
- const0_rtx));
+ gen_int_mode (get_vlmul (vmode), Pmode), altfmt,
+ const0_rtx, const0_rtx));
}
void
@@ -2506,11 +2507,12 @@ rtx
gen_no_side_effects_vsetvl_rtx (machine_mode vmode, rtx vl, rtx avl)
{
unsigned int sew = get_sew (vmode);
+ rtx altfmt = gen_int_mode (ALTFMT_NONE, Pmode);
rtx tail_policy = gen_int_mode (get_prefer_tail_policy (), Pmode);
rtx mask_policy = gen_int_mode (get_prefer_mask_policy (), Pmode);
return gen_vsetvl_no_side_effects (Pmode, vl, avl, gen_int_mode (sew, Pmode),
gen_int_mode (get_vlmul (vmode), Pmode),
- tail_policy, mask_policy);
+ altfmt, tail_policy, mask_policy);
}
/* GET VL * 2 rtx. */
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 5c68f3a690c..e64729b4adf 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -27,6 +27,7 @@
#include "tm_p.h"
#include "memmodel.h"
#include "insn-codes.h"
+#include "insn-attr.h"
#include "optabs.h"
#include "recog.h"
#include "expr.h"
@@ -109,6 +110,9 @@ public:
e.add_input_operand (Pmode, gen_int_mode (get_vlmul (e8_mode), Pmode));
}
+ /* ALTFMT_NONE. */
+ e.add_input_operand (Pmode, gen_int_mode (ALTFMT_NONE, Pmode));
+
/* TAIL_ANY. */
e.add_input_operand (Pmode,
gen_int_mode (get_prefer_tail_policy (), Pmode));
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index e2ba8e1c3d1..c62295ee89b 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -1288,15 +1288,17 @@ public:
avl = GEN_INT (0);
rtx sew = gen_int_mode (get_sew (), Pmode);
rtx vlmul = gen_int_mode (get_vlmul (), Pmode);
+ rtx altfmt = const0_rtx;
rtx ta = gen_int_mode (get_ta (), Pmode);
rtx ma = gen_int_mode (get_ma (), Pmode);
if (change_vtype_only_p ())
- return gen_vsetvl_vtype_change_only (sew, vlmul, ta, ma);
+ return gen_vsetvl_vtype_change_only (sew, vlmul, altfmt, ta, ma);
else if (has_vl () && !ignore_vl)
- return gen_vsetvl (Pmode, get_vl (), avl, sew, vlmul, ta, ma);
+ return gen_vsetvl (Pmode, get_vl (), avl, sew, vlmul, altfmt, ta, ma);
else
- return gen_vsetvl_discard_result (Pmode, avl, sew, vlmul, ta, ma);
+ return gen_vsetvl_discard_result (Pmode, avl, sew, vlmul, altfmt, ta,
+ ma);
}
/* Return true that the non-AVL operands of THIS will be modified
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 219ecdac68b..e76f6a5f277 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -60,6 +60,10 @@
(const_string "true")]
(const_string "false")))
+;; Alternate FP8 format requirement. Most instructions do not care.
+(define_attr "altfmt" "none,alt,any"
+ (const_string "any"))
+
;; True if the type is RVV instructions that include VL
;; global status register in the use op list.
;; The instruction need vector length to be specified is set
@@ -1667,8 +1671,9 @@
;; operands[1]: AVL.
;; operands[2]: SEW
;; operands[3]: LMUL
-;; operands[4]: Tail policy 0 or 1 (undisturbed/agnostic)
-;; operands[5]: Mask policy 0 or 1 (undisturbed/agnostic)
+;; operands[4]: ALTFMT 0 or 1 (none/alt)
+;; operands[5]: Tail policy 0 or 1 (undisturbed/agnostic)
+;; operands[6]: Mask policy 0 or 1 (undisturbed/agnostic)
;; We define 2 types of "vsetvl*" instruction patterns:
@@ -1760,7 +1765,8 @@
(match_operand 2 "const_int_operand" "i")
(match_operand 3 "const_int_operand" "i")
(match_operand 4 "const_int_operand" "i")
- (match_operand 5 "const_int_operand" "i")] UNSPEC_VSETVL))
+ (match_operand 5 "const_int_operand" "i")
+ (match_operand 6 "const_int_operand" "i")] UNSPEC_VSETVL))
(set (reg:SI VL_REGNUM)
(unspec:SI [(match_dup 1)
(match_dup 2)
@@ -1769,15 +1775,18 @@
(unspec:SI [(match_dup 2)
(match_dup 3)
(match_dup 4)
- (match_dup 5)] UNSPEC_VSETVL))]
+ (match_dup 5)
+ (match_dup 6)] UNSPEC_VSETVL))]
"TARGET_VECTOR"
- "vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5"
+ "* return INTVAL (operands[4]) ? \"vset%i1vli\\t%0,%1,e%2alt,%m3,t%p5,m%p6\"
: \"vset%i1vli\\t%0,%1,e%2,%m3,t%p5,m%p6\";"
[(set_attr "type" "vsetvl")
(set_attr "mode" "<MODE>")
(set (attr "sew") (symbol_ref "INTVAL (operands[2])"))
(set (attr "vlmul") (symbol_ref "INTVAL (operands[3])"))
- (set (attr "ta") (symbol_ref "INTVAL (operands[4])"))
- (set (attr "ma") (symbol_ref "INTVAL (operands[5])"))])
+ (set (attr "altfmt")
+ (symbol_ref "((enum attr_altfmt) INTVAL (operands[4]))"))
+ (set (attr "ta") (symbol_ref "INTVAL (operands[5])"))
+ (set (attr "ma") (symbol_ref "INTVAL (operands[6])"))])
;; vsetvl zero,zero,vtype instruction.
;; This pattern has no side effects and does not set X0 register.
@@ -1787,15 +1796,18 @@
[(match_operand 0 "const_int_operand" "i")
(match_operand 1 "const_int_operand" "i")
(match_operand 2 "const_int_operand" "i")
- (match_operand 3 "const_int_operand" "i")] UNSPEC_VSETVL))]
+ (match_operand 3 "const_int_operand" "i")
+ (match_operand 4 "const_int_operand" "i")] UNSPEC_VSETVL))]
"TARGET_VECTOR"
- "vsetvli\tzero,zero,e%0,%m1,t%p2,m%p3"
+ "* return INTVAL (operands[2]) ?
\"vsetvli\\tzero,zero,e%0alt,%m1,t%p3,m%p4\" :
\"vsetvli\\tzero,zero,e%0,%m1,t%p3,m%p4\";"
[(set_attr "type" "vsetvl")
(set_attr "mode" "SI")
(set (attr "sew") (symbol_ref "INTVAL (operands[0])"))
(set (attr "vlmul") (symbol_ref "INTVAL (operands[1])"))
- (set (attr "ta") (symbol_ref "INTVAL (operands[2])"))
- (set (attr "ma") (symbol_ref "INTVAL (operands[3])"))])
+ (set (attr "altfmt")
+ (symbol_ref "((enum attr_altfmt) INTVAL (operands[2]))"))
+ (set (attr "ta") (symbol_ref "INTVAL (operands[3])"))
+ (set (attr "ma") (symbol_ref "INTVAL (operands[4])"))])
;; vsetvl zero,rs1,vtype instruction.
;; The reason we need this pattern since we should avoid setting X0 register
@@ -1809,15 +1821,18 @@
(unspec:SI [(match_dup 1)
(match_dup 2)
(match_operand 3 "const_int_operand" "i")
- (match_operand 4 "const_int_operand" "i")] UNSPEC_VSETVL))]
+ (match_operand 4 "const_int_operand" "i")
+ (match_operand 5 "const_int_operand" "i")] UNSPEC_VSETVL))]
"TARGET_VECTOR"
- "vset%i0vli\tzero,%0,e%1,%m2,t%p3,m%p4"
+ "* return INTVAL (operands[3]) ?
\"vset%i0vli\\tzero,%0,e%1alt,%m2,t%p4,m%p5\" :
\"vset%i0vli\\tzero,%0,e%1,%m2,t%p4,m%p5\";"
[(set_attr "type" "vsetvl")
(set_attr "mode" "<MODE>")
(set (attr "sew") (symbol_ref "INTVAL (operands[1])"))
(set (attr "vlmul") (symbol_ref "INTVAL (operands[2])"))
- (set (attr "ta") (symbol_ref "INTVAL (operands[3])"))
- (set (attr "ma") (symbol_ref "INTVAL (operands[4])"))])
+ (set (attr "altfmt")
+ (symbol_ref "((enum attr_altfmt) INTVAL (operands[3]))"))
+ (set (attr "ta") (symbol_ref "INTVAL (operands[4])"))
+ (set (attr "ma") (symbol_ref "INTVAL (operands[5])"))])
;; It's emit by vsetvl/vsetvlmax intrinsics with no side effects.
;; Since we have many optimization passes from "expand" to "reload_completed",
@@ -1828,22 +1843,29 @@
(match_operand 2 "const_int_operand" "i")
(match_operand 3 "const_int_operand" "i")
(match_operand 4 "const_int_operand" "i")
- (match_operand 5 "const_int_operand" "i")] UNSPEC_VSETVL))]
+ (match_operand 5 "const_int_operand" "i")
+ (match_operand 6 "const_int_operand" "i")] UNSPEC_VSETVL))]
"TARGET_VECTOR"
"#"
"&& epilogue_completed"
[(parallel
[(set (match_dup 0)
(unspec:P [(match_dup 1) (match_dup 2) (match_dup 3)
- (match_dup 4) (match_dup 5)] UNSPEC_VSETVL))
+ (match_dup 4) (match_dup 5) (match_dup 6)] UNSPEC_VSETVL))
(set (reg:SI VL_REGNUM)
(unspec:SI [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_VSETVL))
(set (reg:SI VTYPE_REGNUM)
(unspec:SI [(match_dup 2) (match_dup 3) (match_dup 4)
- (match_dup 5)] UNSPEC_VSETVL))])]
+ (match_dup 5) (match_dup 6)] UNSPEC_VSETVL))])]
""
[(set_attr "type" "vsetvl")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "SI")
+ (set (attr "sew") (symbol_ref "INTVAL (operands[2])"))
+ (set (attr "vlmul") (symbol_ref "INTVAL (operands[3])"))
+ (set (attr "altfmt")
+ (symbol_ref "((enum attr_altfmt) INTVAL (operands[4]))"))
+ (set (attr "ta") (symbol_ref "INTVAL (operands[5])"))
+ (set (attr "ma") (symbol_ref "INTVAL (operands[6])"))])
;; This pattern use to combine below two insns and then further remove
;; unnecessary sign_extend operations:
@@ -1872,7 +1894,8 @@
(match_operand 2 "const_int_operand")
(match_operand 3 "const_int_operand")
(match_operand 4 "const_int_operand")
- (match_operand 5 "const_int_operand")] UNSPEC_VSETVL)
0)))]
+ (match_operand 5 "const_int_operand")
+ (match_operand 6 "const_int_operand")] UNSPEC_VSETVL)
0)))]
"TARGET_VECTOR && TARGET_64BIT"
"#"
"&& 1"
@@ -1881,10 +1904,17 @@
(match_dup 2)
(match_dup 3)
(match_dup 4)
- (match_dup 5)] UNSPEC_VSETVL))]
+ (match_dup 5)
+ (match_dup 6)] UNSPEC_VSETVL))]
""
[(set_attr "type" "vsetvl")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "SI")
+ (set (attr "sew") (symbol_ref "INTVAL (operands[2])"))
+ (set (attr "vlmul") (symbol_ref "INTVAL (operands[3])"))
+ (set (attr "altfmt")
+ (symbol_ref "((enum attr_altfmt) INTVAL (operands[4]))"))
+ (set (attr "ta") (symbol_ref "INTVAL (operands[5])"))
+ (set (attr "ma") (symbol_ref "INTVAL (operands[6])"))])
;; RVV machine description matching format
;; (define_insn ""
--
2.34.1
