From: Lino Hsing-Yu Peng <[email protected]>
Add Zvfofp8min narrowing support from FP32 to FP8 by extending builtin
operation typing and generated indices for quad-trunc forms. Hook the new
operations into the RVV builtins and float8 machine description patterns.
gcc/ChangeLog:
* config/riscv/genrvv-type-indexer.cc: Add QUAD_TRUNC_UNSIGNED entries.
* config/riscv/riscv-vector-builtins-bases.cc: Add f32 to f8 quad-trunc
handling.
* config/riscv/riscv-vector-builtins-functions.def: Add f32 to f8
builtins.
* config/riscv/riscv-vector-builtins-shapes.cc: Adjust f8 narrow naming
for f_q.
* config/riscv/riscv-vector-builtins.cc: Add f32_to_f8 operand info.
* config/riscv/riscv-vector-builtins.def: Add f_q op type.
* config/riscv/vector-float8.md: Add f32 to f8 narrowing patterns.
---
gcc/config/riscv/genrvv-type-indexer.cc | 10 +++
.../riscv/riscv-vector-builtins-bases.cc | 30 +++++++++
.../riscv/riscv-vector-builtins-functions.def | 8 +++
.../riscv/riscv-vector-builtins-shapes.cc | 12 ++--
gcc/config/riscv/riscv-vector-builtins.cc | 38 +++++++-----
gcc/config/riscv/riscv-vector-builtins.def | 8 ++-
gcc/config/riscv/vector-float8.md | 62 ++++++++++++++++---
7 files changed, 140 insertions(+), 28 deletions(-)
diff --git a/gcc/config/riscv/genrvv-type-indexer.cc
b/gcc/config/riscv/genrvv-type-indexer.cc
index 040a5aee9ac..533e39ebe58 100644
--- a/gcc/config/riscv/genrvv-type-indexer.cc
+++ b/gcc/config/riscv/genrvv-type-indexer.cc
@@ -274,6 +274,7 @@ main (int argc, const char **argv)
fprintf (fp, " /*SHIFT*/ INVALID,\n");
fprintf (fp, " /*DOUBLE_TRUNC*/ INVALID,\n");
fprintf (fp, " /*QUAD_TRUNC*/ INVALID,\n");
+ fprintf (fp, " /*QUAD_TRUNC_UNSIGNED*/ INVALID,\n");
fprintf (fp, " /*QUAD_EMUL*/ INVALID,\n");
fprintf (fp, " /*QUAD_EMUL_SIGNED*/ INVALID,\n");
fprintf (fp, " /*QUAD_EMUL_UNSIGNED*/ INVALID,\n");
@@ -357,6 +358,9 @@ main (int argc, const char **argv)
same_ratio_eew_type (sew, lmul_log2, sew / 4, unsigned_p,
false)
.c_str ());
+ fprintf (fp, " /*QUAD_TRUNC_UNSIGNED*/ %s,\n",
+ same_ratio_eew_type (sew, lmul_log2, sew / 4, true, false)
+ .c_str ());
fprintf (fp, " /*QUAD_EMUL*/ %s,\n",
inttype (8, lmul_log2 - 1, unsigned_p).c_str ());
fprintf (fp, " /*QUAD_EMUL_SIGNED*/ %s,\n",
@@ -473,6 +477,9 @@ main (int argc, const char **argv)
fprintf (fp, " /*DOUBLE_TRUNC*/ %s,\n",
same_ratio_eew_type (16, lmul_log2, 8, false, true).c_str ());
fprintf (fp, " /*QUAD_TRUNC*/ INVALID,\n");
+ fprintf (
+ fp, " /*QUAD_TRUNC_UNSIGNED*/ %s,\n",
+ same_ratio_eew_type (16, lmul_log2, 16 / 4, true, false).c_str ());
fprintf (fp, " /*QUAD_EMUL*/ INVALID,\n");
fprintf (fp, " /*QUAD_EMUL_SIGNED*/ INVALID,\n");
fprintf (fp, " /*QUAD_EMUL_UNSIGNED*/ INVALID,\n");
@@ -555,6 +562,9 @@ main (int argc, const char **argv)
same_ratio_eew_type (sew, lmul_log2, sew / 2, false, true)
.c_str ());
fprintf (fp, " /*QUAD_TRUNC*/ INVALID,\n");
+ fprintf (fp, " /*QUAD_TRUNC_UNSIGNED*/ %s,\n",
+ same_ratio_eew_type (sew, lmul_log2, sew / 4, true, false)
+ .c_str ());
fprintf (fp, " /*QUAD_EMUL*/ INVALID,\n");
fprintf (fp, " /*QUAD_EMUL_SIGNED*/ INVALID,\n");
fprintf (fp, " /*QUAD_EMUL_UNSIGNED*/ INVALID,\n");
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 3fa3ebb5d14..5c68f3a690c 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1620,6 +1620,20 @@ public:
return e.use_exact_insn (code_for_pred_trunc (e.vector_mode ()));
}
}
+ if (e.op_info->op == OP_TYPE_f_q)
+ {
+ switch (get_altfmt (e))
+ {
+ case F8E4M3:
+ return e.use_exact_insn (
+ code_for_pred_quad_trunc_to (e.vector_mode (), UNSPEC_F8E4M3));
+ case F8E5M2:
+ return e.use_exact_insn (
+ code_for_pred_quad_trunc_to (e.vector_mode (), UNSPEC_F8E5M2));
+ default:
+ gcc_unreachable ();
+ }
+ }
if (e.op_info->op == OP_TYPE_x_w)
return e.use_exact_insn (code_for_pred_narrow (FLOAT, e.arg_mode (0)));
if (e.op_info->op == OP_TYPE_xu_w)
@@ -1656,6 +1670,22 @@ public:
break;
}
}
+ if (e.op_info->op == OP_TYPE_f_q)
+ {
+ switch (get_altfmt (e))
+ {
+ case F8E4M3:
+ return e.use_exact_insn (
+ code_for_pred_quad_trunc_to (e.vector_mode (),
+ UNSPEC_F8E4M3_SAT));
+ case F8E5M2:
+ return e.use_exact_insn (
+ code_for_pred_quad_trunc_to (e.vector_mode (),
+ UNSPEC_F8E5M2_SAT));
+ default:
+ gcc_unreachable ();
+ }
+ }
gcc_unreachable ();
}
};
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 49ad8585933..ed34dfa0dfe 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -775,13 +775,21 @@ DEF_RVV_FUNCTION (vfwcvt_f, alu_f8e4m3, full_preds,
f8_to_bf16_f_v_ops)
DEF_RVV_FUNCTION (vfwcvt_f, alu_f8e5m2, full_preds, f8_to_bf16_f_v_ops)
DEF_RVV_FUNCTION (vfncvt_f, narrow_alu_f8e4m3, full_preds, bf16_to_f8_f_w_ops)
DEF_RVV_FUNCTION (vfncvt_f, narrow_alu_f8e5m2, full_preds, bf16_to_f8_f_w_ops)
+DEF_RVV_FUNCTION (vfncvt_f, narrow_alu_f8e4m3, full_preds, f32_to_f8_f_q_ops)
+DEF_RVV_FUNCTION (vfncvt_f, narrow_alu_f8e5m2, full_preds, f32_to_f8_f_q_ops)
DEF_RVV_FUNCTION (vfncvt_sat_f, narrow_alu_f8e4m3, full_preds,
bf16_to_f8_f_w_ops)
DEF_RVV_FUNCTION (vfncvt_sat_f, narrow_alu_f8e5m2, full_preds,
bf16_to_f8_f_w_ops)
+DEF_RVV_FUNCTION (vfncvt_sat_f, narrow_alu_f8e4m3, full_preds,
f32_to_f8_f_q_ops)
+DEF_RVV_FUNCTION (vfncvt_sat_f, narrow_alu_f8e5m2, full_preds,
f32_to_f8_f_q_ops)
DEF_RVV_FUNCTION (vfncvt_f_frm, narrow_alu_frm_f8e4m3, full_preds,
bf16_to_f8_f_w_ops)
DEF_RVV_FUNCTION (vfncvt_f_frm, narrow_alu_frm_f8e5m2, full_preds,
bf16_to_f8_f_w_ops)
+DEF_RVV_FUNCTION (vfncvt_f_frm, narrow_alu_frm_f8e4m3, full_preds,
f32_to_f8_f_q_ops)
+DEF_RVV_FUNCTION (vfncvt_f_frm, narrow_alu_frm_f8e5m2, full_preds,
f32_to_f8_f_q_ops)
DEF_RVV_FUNCTION (vfncvt_sat_f_frm, narrow_alu_frm_f8e4m3, full_preds,
bf16_to_f8_f_w_ops)
DEF_RVV_FUNCTION (vfncvt_sat_f_frm, narrow_alu_frm_f8e5m2, full_preds,
bf16_to_f8_f_w_ops)
+DEF_RVV_FUNCTION (vfncvt_sat_f_frm, narrow_alu_frm_f8e4m3, full_preds,
f32_to_f8_f_q_ops)
+DEF_RVV_FUNCTION (vfncvt_sat_f_frm, narrow_alu_frm_f8e5m2, full_preds,
f32_to_f8_f_q_ops)
#undef REQUIRED_EXTENSIONS
/* Zvfbfwma */
diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
index 8385a49f517..d593ff28ce0 100644
--- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
@@ -824,9 +824,12 @@ build_f8_narrow_name (function_builder &b, const
function_instance &instance,
vector_type_index vti
= instance.op_info->args[0].get_function_type_index (
instance.type.index);
- const char *src_scalar
- = vti == VECTOR_TYPE_INVALID ? nullptr : type_suffixes[vti].scalar;
- b.append_name (src_scalar ? src_scalar : "_bf16");
+ if (instance.op_info->op == OP_TYPE_f_w)
+ {
+ const char *src_scalar
+ = vti == VECTOR_TYPE_INVALID ? nullptr : type_suffixes[vti].scalar;
+ b.append_name (src_scalar ? src_scalar : "_bf16");
+ }
b.append_name ("_");
b.append_name (altfmt);
}
@@ -836,7 +839,8 @@ build_f8_narrow_name (function_builder &b, const
function_instance &instance,
vector_type_index vti
= instance.op_info->args[0].get_function_type_index (
instance.type.index);
- if (vti != VECTOR_TYPE_INVALID)
+ /* Additional type suffix before output type suffix. */
+ if (vti != VECTOR_TYPE_INVALID && instance.op_info->op != OP_TYPE_f_q)
b.append_name (type_suffixes[vti].vector);
append_f8_suffix (b,
instance.op_info->ret.get_function_type_index (
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
b/gcc/config/riscv/riscv-vector-builtins.cc
index c671b133c85..ed5af47c3a2 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -2067,6 +2067,14 @@ static CONSTEXPR const rvv_op_info bf16_to_f8_f_w_ops
RVV_BASE_double_trunc_unsigned_vector), /* Return type */
v_args /* Args */};
+/* A static operand information for vector_type func (vector_type)
+ * function registration. */
+static CONSTEXPR const rvv_op_info f32_to_f8_f_q_ops
+ = {f32_ops, /* Types */
+ OP_TYPE_f_q, /* Suffix */
+ rvv_arg_type_info (RVV_BASE_quad_trunc_unsigned_vector), /* Return type */
+ v_args /* Args */};
+
/* A static operand information for vector_type func (vector_type)
* function registration. */
static CONSTEXPR const rvv_op_info f8_to_bf16_f_v_ops
@@ -3468,20 +3476,21 @@ static CONSTEXPR const rvv_op_info sf_vc_v_fvw_ops
static CONSTEXPR const function_type_info function_types[] = {
#define DEF_RVV_TYPE_INDEX(
\
VECTOR, MASK, SIGNED, UNSIGNED, SIGNED_EEW8_INDEX, EEW8_INDEX, EEW16_INDEX,
\
- EEW32_INDEX, EEW64_INDEX, SHIFT, DOUBLE_TRUNC, QUAD_TRUNC, QUAD_EMUL,
\
- QUAD_EMUL_SIGNED, QUAD_EMUL_UNSIGNED, QUAD_FIX, QUAD_FIX_SIGNED,
\
- QUAD_FIX_UNSIGNED, OCT_TRUNC, DOUBLE_TRUNC_SCALAR, DOUBLE_TRUNC_SIGNED,
\
- DOUBLE_TRUNC_UNSIGNED, DOUBLE_TRUNC_UNSIGNED_SCALAR,
\
- DOUBLE_TRUNC_BFLOAT_SCALAR, DOUBLE_TRUNC_BFLOAT, DOUBLE_TRUNC_FLOAT, FLOAT,
\
- LMUL1, WLMUL1, QLMUL1, QLMUL1_SIGNED, QLMUL1_UNSIGNED, XFQF, EEW8_INTERPRET,
\
- EEW16_INTERPRET, EEW32_INTERPRET, EEW64_INTERPRET, BOOL1_INTERPRET,
\
- BOOL2_INTERPRET, BOOL4_INTERPRET, BOOL8_INTERPRET, BOOL16_INTERPRET,
\
- BOOL32_INTERPRET, BOOL64_INTERPRET, SIGNED_EEW8_LMUL1_INTERPRET,
\
- SIGNED_EEW16_LMUL1_INTERPRET, SIGNED_EEW32_LMUL1_INTERPRET,
\
- SIGNED_EEW64_LMUL1_INTERPRET, UNSIGNED_EEW8_LMUL1_INTERPRET,
\
- UNSIGNED_EEW16_LMUL1_INTERPRET, UNSIGNED_EEW32_LMUL1_INTERPRET,
\
- UNSIGNED_EEW64_LMUL1_INTERPRET, X2, X2_VLMUL_EXT, X4_VLMUL_EXT,
X8_VLMUL_EXT,\
- X16_VLMUL_EXT, X32_VLMUL_EXT, X64_VLMUL_EXT, TUPLE_SUBPART)
\
+ EEW32_INDEX, EEW64_INDEX, SHIFT, DOUBLE_TRUNC, QUAD_TRUNC,
\
+ QUAD_TRUNC_UNSIGNED, QUAD_EMUL, QUAD_EMUL_SIGNED, QUAD_EMUL_UNSIGNED,
\
+ QUAD_FIX, QUAD_FIX_SIGNED, QUAD_FIX_UNSIGNED, OCT_TRUNC,
\
+ DOUBLE_TRUNC_SCALAR, DOUBLE_TRUNC_SIGNED, DOUBLE_TRUNC_UNSIGNED,
\
+ DOUBLE_TRUNC_UNSIGNED_SCALAR, DOUBLE_TRUNC_BFLOAT_SCALAR,
\
+ DOUBLE_TRUNC_BFLOAT, DOUBLE_TRUNC_FLOAT, FLOAT, LMUL1, WLMUL1, QLMUL1,
\
+ QLMUL1_SIGNED, QLMUL1_UNSIGNED, XFQF, EEW8_INTERPRET, EEW16_INTERPRET,
\
+ EEW32_INTERPRET, EEW64_INTERPRET, BOOL1_INTERPRET, BOOL2_INTERPRET,
\
+ BOOL4_INTERPRET, BOOL8_INTERPRET, BOOL16_INTERPRET, BOOL32_INTERPRET,
\
+ BOOL64_INTERPRET, SIGNED_EEW8_LMUL1_INTERPRET, SIGNED_EEW16_LMUL1_INTERPRET,
\
+ SIGNED_EEW32_LMUL1_INTERPRET, SIGNED_EEW64_LMUL1_INTERPRET,
\
+ UNSIGNED_EEW8_LMUL1_INTERPRET, UNSIGNED_EEW16_LMUL1_INTERPRET,
\
+ UNSIGNED_EEW32_LMUL1_INTERPRET, UNSIGNED_EEW64_LMUL1_INTERPRET, X2,
\
+ X2_VLMUL_EXT, X4_VLMUL_EXT, X8_VLMUL_EXT, X16_VLMUL_EXT, X32_VLMUL_EXT,
\
+ X64_VLMUL_EXT, TUPLE_SUBPART)
\
{
\
VECTOR_TYPE_##VECTOR,
\
VECTOR_TYPE_INVALID,
\
@@ -3506,6 +3515,7 @@ static CONSTEXPR const function_type_info
function_types[] = {
VECTOR_TYPE_##SHIFT,
\
VECTOR_TYPE_##DOUBLE_TRUNC,
\
VECTOR_TYPE_##QUAD_TRUNC,
\
+ VECTOR_TYPE_##QUAD_TRUNC_UNSIGNED,
\
VECTOR_TYPE_##QUAD_EMUL,
\
VECTOR_TYPE_##QUAD_EMUL_SIGNED,
\
VECTOR_TYPE_##QUAD_EMUL_UNSIGNED,
\
diff --git a/gcc/config/riscv/riscv-vector-builtins.def
b/gcc/config/riscv/riscv-vector-builtins.def
index 01e7409f5dc..eebc8d7c001 100644
--- a/gcc/config/riscv/riscv-vector-builtins.def
+++ b/gcc/config/riscv/riscv-vector-builtins.def
@@ -70,10 +70,10 @@ along with GCC; see the file COPYING3. If not see
#ifndef DEF_RVV_TYPE_INDEX
#define DEF_RVV_TYPE_INDEX(
\
VECTOR, MASK, SIGNED, UNSIGNED, SIGNED_EEW8_INDEX, EEW8_INDEX, EEW16_INDEX,
\
- EEW32_INDEX, EEW64_INDEX, SHIFT, DOUBLE_TRUNC, QUAD_TRUNC, QUAD_EMUL,
\
- QUAD_EMUL_SIGNED, QUAD_EMUL_UNSIGNED, QUAD_FIX, QUAD_FIX_SIGNED,
\
+ EEW32_INDEX, EEW64_INDEX, SHIFT, DOUBLE_TRUNC, QUAD_TRUNC,
QUAD_TRUNC_UNSIGNED, \
+ QUAD_EMUL, QUAD_EMUL_SIGNED, QUAD_EMUL_UNSIGNED, QUAD_FIX, QUAD_FIX_SIGNED,
\
QUAD_FIX_UNSIGNED, OCT_TRUNC, DOUBLE_TRUNC_SCALAR, DOUBLE_TRUNC_SIGNED,
\
- DOUBLE_TRUNC_UNSIGNED, DOUBLE_TRUNC_UNSIGNED_SCALAR,
\
+ DOUBLE_TRUNC_UNSIGNED, DOUBLE_TRUNC_UNSIGNED_SCALAR, \
DOUBLE_TRUNC_BFLOAT_SCALAR, DOUBLE_TRUNC_BFLOAT, DOUBLE_TRUNC_FLOAT, FLOAT,
\
LMUL1, WLMUL1, QLMUL1, QLMUL1_SIGNED, QLMUL1_UNSIGNED, XFQF, EEW8_INTERPRET,
\
EEW16_INTERPRET, EEW32_INTERPRET, EEW64_INTERPRET, BOOL1_INTERPRET,
\
@@ -633,6 +633,7 @@ DEF_RVV_OP_TYPE (f)
DEF_RVV_OP_TYPE (f_v)
DEF_RVV_OP_TYPE (xu_v)
DEF_RVV_OP_TYPE (f_w)
+DEF_RVV_OP_TYPE (f_q)
DEF_RVV_OP_TYPE (xu_w)
DEF_RVV_OP_TYPE (s)
DEF_RVV_OP_TYPE (4x8x4)
@@ -708,6 +709,7 @@ DEF_RVV_BASE_TYPE (eew64_index, get_vector_type (type_idx))
DEF_RVV_BASE_TYPE (shift_vector, get_vector_type (type_idx))
DEF_RVV_BASE_TYPE (double_trunc_vector, get_vector_type (type_idx))
DEF_RVV_BASE_TYPE (quad_trunc_vector, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (quad_trunc_unsigned_vector, get_vector_type (type_idx))
DEF_RVV_BASE_TYPE (quad_emul_vector, get_vector_type (type_idx))
DEF_RVV_BASE_TYPE (quad_emul_signed_vector, get_vector_type (type_idx))
DEF_RVV_BASE_TYPE (quad_emul_unsigned_vector, get_vector_type (type_idx))
diff --git a/gcc/config/riscv/vector-float8.md
b/gcc/config/riscv/vector-float8.md
index 423b490b811..20c656a948b 100644
--- a/gcc/config/riscv/vector-float8.md
+++ b/gcc/config/riscv/vector-float8.md
@@ -26,6 +26,14 @@
(RVVMF4BF "TARGET_ZVFOFP8MIN && TARGET_ZVFBFMIN && TARGET_MIN_VLEN > 32")
])
+(define_mode_iterator VWEXT4_ZVFOFP8MIN [
+ (RVVM8SF "TARGET_ZVFOFP8MIN")
+ (RVVM4SF "TARGET_ZVFOFP8MIN")
+ (RVVM2SF "TARGET_ZVFOFP8MIN")
+ (RVVM1SF "TARGET_ZVFOFP8MIN")
+ (RVVMF2SF "TARGET_ZVFOFP8MIN")
+])
+
(define_mode_attr VBF_DOUBLE_TRUNC [
(RVVM8BF "RVVM4QI")
(RVVM4BF "RVVM2QI")
@@ -35,8 +43,22 @@
(RVVMF4BF "RVVMF8QI")
])
-(define_int_iterator ALTFMT [UNSPEC_F8E4M3 UNSPEC_F8E5M2 UNSPEC_F8E4M3_SAT
UNSPEC_F8E5M2_SAT])
-(define_int_attr altfmt
+(define_mode_attr VF_QUAD_TRUNC [
+ (RVVM8SF "RVVM2QI")
+ (RVVM4SF "RVVM1QI")
+ (RVVM2SF "RVVMF2QI")
+ (RVVM1SF "RVVMF4QI")
+ (RVVMF2SF "RVVMF8QI")
+])
+
+(define_int_iterator ALTFMT_BASE [UNSPEC_F8E4M3 UNSPEC_F8E5M2])
+(define_int_iterator ALTFMT_SAT [UNSPEC_F8E4M3 UNSPEC_F8E5M2 UNSPEC_F8E4M3_SAT
UNSPEC_F8E5M2_SAT])
+
+(define_int_attr altfmt_base
+ [(UNSPEC_F8E4M3 "f8e4m3")
+ (UNSPEC_F8E5M2 "f8e5m2")])
+
+(define_int_attr altfmt_sat
[(UNSPEC_F8E4M3 "f8e4m3")
(UNSPEC_F8E5M2 "f8e5m2")
(UNSPEC_F8E4M3_SAT "f8e4m3_sat")
@@ -50,7 +72,7 @@
;; Zvfofp8min extension: FP8 to BF16 widening conversions.
-(define_insn "@pred_extend_<altfmt>_to_<mode>"
+(define_insn "@pred_extend_<altfmt_base>_to_<mode>"
[(set (match_operand:VWEXTF_ZVFOFP8MIN 0 "register_operand" "=&vr,
&vr")
(if_then_else:VWEXTF_ZVFOFP8MIN
(unspec:<VM>
@@ -63,8 +85,8 @@
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(unspec:VWEXTF_ZVFOFP8MIN
[(float_extend:VWEXTF_ZVFOFP8MIN
- (match_operand:<VBF_DOUBLE_TRUNC> 3 "register_operand" " vr,
vr"))] ALTFMT)
- (match_operand:VWEXTF_ZVFOFP8MIN 2 "vector_merge_operand" " vu,
0")))]
+ (match_operand:<VBF_DOUBLE_TRUNC> 3 "register_operand" " vr,
vr"))] ALTFMT_BASE)
+ (match_operand:VWEXTF_ZVFOFP8MIN 2 "vector_merge_operand" "
vu, 0")))]
"TARGET_VECTOR && TARGET_ZVFOFP8MIN && TARGET_ZVFBFMIN"
"vfwcvtbf16.f.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtbf16")
@@ -72,7 +94,7 @@
;; Zvfofp8min extension: BF16 to FP8 narrowing conversions.
-(define_insn "@pred_trunc_<mode>_to_<altfmt>"
+(define_insn "@pred_trunc_<mode>_to_<altfmt_sat>"
[(set (match_operand:<VBF_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr,
vr, &vr, &vr")
(if_then_else:<VBF_DOUBLE_TRUNC>
(unspec:<VM>
@@ -87,7 +109,7 @@
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(unspec:<VBF_DOUBLE_TRUNC>
[(float_truncate:<VBF_DOUBLE_TRUNC>
- (match_operand:VWEXTF_ZVFOFP8MIN 3 "register_operand" " 0,
0, 0, 0, vr, vr"))] ALTFMT)
+ (match_operand:VWEXTF_ZVFOFP8MIN 3 "register_operand" " 0,
0, 0, 0, vr, vr"))] ALTFMT_SAT)
(match_operand:<VBF_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0,
vu, 0, vu, 0")))]
"TARGET_VECTOR && TARGET_ZVFOFP8MIN && TARGET_ZVFBFMIN"
"vfncvtbf16<sat>.f.f.w\t%0,%3%p1"
@@ -95,3 +117,29 @@
(set_attr "mode" "<VBF_DOUBLE_TRUNC>")
(set (attr "frm_mode")
(symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
+
+;; Zvfofp8min extension: F32 to FP8 narrowing conversions.
+
+(define_insn "@pred_quad_trunc_<mode>_to_<altfmt_sat>"
+ [(set (match_operand:<VF_QUAD_TRUNC> 0 "register_operand" "=vd, vd, vr,
vr, &vr, &vr")
+ (if_then_else:<VF_QUAD_TRUNC>
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,
vm,Wc1,Wc1,vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK, rK,
rK, rK, rK")
+ (match_operand 5 "const_int_operand" " i, i, i,
i, i, i")
+ (match_operand 6 "const_int_operand" " i, i, i,
i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i,
i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i,
i, i, i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+ (unspec:<VF_QUAD_TRUNC>
+ [(float_truncate:<VF_QUAD_TRUNC>
+ (match_operand:VWEXT4_ZVFOFP8MIN 3 "register_operand" " 0, 0,
0, 0, vr, vr"))] ALTFMT_SAT)
+ (match_operand:<VF_QUAD_TRUNC> 2 "vector_merge_operand" " vu, 0, vu,
0, vu, 0")))]
+ "TARGET_VECTOR && TARGET_ZVFOFP8MIN"
+ "vfncvt<sat>.f.f.q\t%0,%3%p1"
+ [(set_attr "type" "vfncvtbf16")
+ (set_attr "mode" "<VF_QUAD_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
--
2.34.1
