Hi!
On Mon, May 18, 2026 at 09:04:55PM +0530, Surya Kumari Jangala wrote:
> Can you please add a testcase? The patch looks fine.
> I cannot approve it though.
But I can. The patch is okay for trunk. Maybe improve the comments a
little, see further on.
> On 18/05/26 3:08 AM, Steve Markgraf wrote:
> > The MPC8xx PowerQUICC family only implements full 'sync', 'lwsync'
> > is not yet supported, same situation as for E500 cores.
Yeah. Do after this patch we handle all CPUs that do not handle lwsync
reasonably? ("Classic" CPUs work fine, they actually ignore all the SBZ
bits most of the time, like instructions bits 6..20 in sync insns -- so
they actually do the equivalent of hwsync whenever there is an lwsync,
but that is a valid implementation for it, just perhaps not optimally
fast :-) )
> > -/* E500 cores only support plain "sync", not lwsync. */
> > +/* E500 and MPC8xx cores only support plain "sync", not lwsync. */
> > #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \
> > - || rs6000_cpu == PROCESSOR_PPC8548)
> > + || rs6000_cpu == PROCESSOR_PPC8548 \
> > + || rs6000_cpu == PROCESSOR_MPCCORE)
They only support sync insns with all the should-be-zero bits actually
zero. Both "lwsync" and "hwsync" are sync insns. Both in common sense,
but also both of those are "sync" when run on a classic CPU. Some of
those CPUs check if all SBZ bits actually are zero, and punish the user
if not.
Segher
