Hi!
On Mon, May 18, 2026 at 06:06:40PM +0200, Steve Markgraf wrote:
> The MPC8xx PowerQUICC family only implements full 'sync', 'lwsync'
> is not yet supported, same situation as for E500 cores.
>
> Fix emitting 'lwsync' instructions by adding PROCESSOR_MPCCORE
> to the TARGET_NO_LWSYNC define.
>
> Encountered an illegal instruction crash (in libstdc++ atomics) and
> verified the fix on actual MPC860 hardware.
>
> Minimal test:
>
> $ cat test.c
> #include <stdatomic.h>
> atomic_int counter;
> void store_release(int val) {
> atomic_store_explicit(&counter, val, memory_order_release);
> }
>
> $ powerpc-linux-gnu-gcc -mcpu=860 -msoft-float -O2 -S -o- test.c | grep sync
> lwsync <-- should be sync
>
> $ powerpc-linux-gnu-gcc -mcpu=8540 -msoft-float -O2 -S -o- test.c | grep
> sync
> sync <-- correct (TARGET_NO_LWSYNC already covers E500/8540)
>
> gcc/ChangeLog:
>
> * config/rs6000/rs6000.h (TARGET_NO_LWSYNC): Add
> PROCESSOR_MPCCORE.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/powerpc/atomic-mpc860.c: New test.
> ---
> Hi Surya,
>
> I've added a simple testcase, here's V2 of the patch.
>
> Regards,
> Steve
>
> gcc/config/rs6000/rs6000.h | 5 +++--
> gcc/testsuite/gcc.target/powerpc/atomic-mpc860.c | 14 ++++++++++++++
> 2 files changed, 17 insertions(+), 2 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/powerpc/atomic-mpc860.c
>
> diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
> index 2d3016db5..a6ce0560f 100644
> --- a/gcc/config/rs6000/rs6000.h
> +++ b/gcc/config/rs6000/rs6000.h
> @@ -533,9 +533,10 @@ extern int rs6000_vector_align[];
> || TARGET_VSX \
> || TARGET_HARD_FLOAT)
>
> -/* E500 cores only support plain "sync", not lwsync. */
> +/* E500 and MPC8xx cores only support plain "sync", not lwsync. */
> #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \
> - || rs6000_cpu == PROCESSOR_PPC8548)
> + || rs6000_cpu == PROCESSOR_PPC8548 \
> + || rs6000_cpu == PROCESSOR_MPCCORE)
>
>
> /* Which machine supports the various reciprocal estimate instructions. */
> diff --git a/gcc/testsuite/gcc.target/powerpc/atomic-mpc860.c
> b/gcc/testsuite/gcc.target/powerpc/atomic-mpc860.c
> new file mode 100644
> index 000000000..39598b137
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/atomic-mpc860.c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile { target powerpc*-*-* } } */
> +/* { dg-options "-mcpu=860 -msoft-float -O2" } */
Is -msoft-float necessary to compile at all? Otherwise please leave it
out.
> +/* Test that MPC8xx (MPCCORE) processors do not emit lwsync, since the
> + MPC8xx core does not support this instruction. It should use sync
> + instead. */
It isn't the processor that emits the code :-) "Check that _we_ do not
emit lwsync when targeting mpccore".
> +void
> +store_release (int *ptr, int val)
> +{
> + __atomic_store_n (ptr, val, __ATOMIC_RELEASE);
> +}
> +
> +/* { dg-final { scan-assembler-not "lwsync" } } */
+/* { dg-final { scan-assembler-not "\mlwsync\M" } } */
is a bit more robust. Perhaps you could even use "lwsync" in the file
name of the test that way ;-)
Segher
