On Mon, May 18, 2026 at 08:20:54PM +0200, Steve Markgraf wrote: > The MPC8xx PowerQUICC family only implements full 'sync', 'lwsync' > is not yet supported. The CPU actually checks that the > should-be-zero bits of the sync instruction are zero, and faults > otherwise - same situation as for E500 cores.
> Fix emitting 'lwsync' instructions by adding PROCESSOR_MPCCORE > to the TARGET_NO_LWSYNC define. Perfect, thank you! The patch is okay for trunk. Do you need/want backports as well? > $ powerpc-linux-gnu-gcc -mcpu=860 -O2 -S -o- test.c | grep sync > lwsync <-- should be sync > > $ powerpc-linux-gnu-gcc -mcpu=8540 -O2 -S -o- test.c | grep sync > sync <-- correct (TARGET_NO_LWSYNC already covers E500/8540) Yup, a nice and succinct explanation :-) > gcc/ChangeLog: > > * config/rs6000/rs6000.h (TARGET_NO_LWSYNC): Add > PROCESSOR_MPCCORE. Please keep things on one line. Do not break lines easrly! Changelog lines are 80 positions (the leading tab is eight of-em). > Unfortunately > the test fails with lwsync in the filename even with \m\M, so I > kept the filename. Yeah, \m is start of a word (and \M is end), and a word is the maximum extent of word characters (alnum and underscore). So maybe name the file something like "blalblablabab_lwsync" :-) (So that the "l" in that is not the beginning of a word!) > I did some more research, and to my knowledge now all cores that > fault on L=1 are covered with this patch. What does "L=1" mean? Oh, bit 8..10 in the sync insn? Gotcha. Thanks, Segher
