[PATCH v1 1/4] RISC-V: Allow RVV register overlap for vwcvt[u].x.x.v

[pan2 . li]

From: Pan Li <pan2...@intel.com>

Like v[sz]ext.vf8, allow the rvv register overlap
for vwcvt[u].x.x.v.

gcc/ChangeLog:

        * config/riscv/vector.md: Leverage Wvr constraint.

Signed-off-by: Pan Li <pan2...@intel.com>
---
 gcc/config/riscv/vector.md | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index dca6108e0aa..0ca589bf042 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -4349,22 +4349,22 @@ (define_insn "@pred_widen_mulsu<mode>_scalar"
 
 ;; vwcvt<u>.x.x.v
 (define_insn "@pred_<optab><mode>"
-  [(set (match_operand:VWEXTI 0 "register_operand"                  "=&vr,&vr")
+  [(set (match_operand:VWEXTI 0 "register_operand"                 "=vr, vr, 
vd, vd")
        (if_then_else:VWEXTI
          (unspec:<VM>
-           [(match_operand:<VM> 1 "vector_mask_operand"           
"vmWc1,vmWc1")
-            (match_operand 4 "vector_length_operand"              "  rvl,  
rvl")
-            (match_operand 5 "const_int_operand"                  "    i,    
i")
-            (match_operand 6 "const_int_operand"                  "    i,    
i")
-            (match_operand 7 "const_int_operand"                  "    i,    
i")
+           [(match_operand:<VM> 1 "vector_mask_operand"           "Wc1,Wc1, 
vm, vm")
+            (match_operand 4 "vector_length_operand"              
"rvl,rvl,rvl,rvl")
+            (match_operand 5 "const_int_operand"                  "  i,  i,  
i,  i")
+            (match_operand 6 "const_int_operand"                  "  i,  i,  
i,  i")
+            (match_operand 7 "const_int_operand"                  "  i,  i,  
i,  i")
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (plus:VWEXTI
            (any_extend:VWEXTI
-             (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "   vr,   
vr"))
+             (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" 
"Wvr,Wvr,Wvr,Wvr"))
            (vec_duplicate:VWEXTI
              (reg:<VEL> X0_REGNUM)))
-         (match_operand:VWEXTI 2 "vector_merge_operand"           "   vu,    
0")))]
+         (match_operand:VWEXTI 2 "vector_merge_operand"           " vu,  0, 
vu,  0")))]
   "TARGET_VECTOR"
   "vwcvt<u>.x.x.v\t%0,%3%p1"
   [(set_attr "type" "viwalu")
-- 
2.43.0