From: Pan Li <[email protected]>
Add test cases for vwcvtu.x.x.v register group overlap, please
note it is not overlap as much as possible.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i16-m1.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i16-m2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i16-m4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i16-mf2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i16-mf4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i32-m1.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i32-m2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i32-m4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i32-mf2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-m1.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-m2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-m4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-mf2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-mf4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-mf8.c: New test.
Signed-off-by: Pan Li <[email protected]>
---
.../rvv/autovec/group_overlap/vwcvtu-i16-m1.c | 17 ++++++++++
.../rvv/autovec/group_overlap/vwcvtu-i16-m2.c | 17 ++++++++++
.../rvv/autovec/group_overlap/vwcvtu-i16-m4.c | 17 ++++++++++
.../autovec/group_overlap/vwcvtu-i16-mf2.c | 31 +++++++++++++++++++
.../autovec/group_overlap/vwcvtu-i16-mf4.c | 31 +++++++++++++++++++
.../rvv/autovec/group_overlap/vwcvtu-i32-m1.c | 17 ++++++++++
.../rvv/autovec/group_overlap/vwcvtu-i32-m2.c | 17 ++++++++++
.../rvv/autovec/group_overlap/vwcvtu-i32-m4.c | 17 ++++++++++
.../autovec/group_overlap/vwcvtu-i32-mf2.c | 31 +++++++++++++++++++
.../rvv/autovec/group_overlap/vwcvtu-i8-m1.c | 17 ++++++++++
.../rvv/autovec/group_overlap/vwcvtu-i8-m2.c | 17 ++++++++++
.../rvv/autovec/group_overlap/vwcvtu-i8-m4.c | 17 ++++++++++
.../rvv/autovec/group_overlap/vwcvtu-i8-mf2.c | 31 +++++++++++++++++++
.../rvv/autovec/group_overlap/vwcvtu-i8-mf4.c | 31 +++++++++++++++++++
.../rvv/autovec/group_overlap/vwcvtu-i8-mf8.c | 31 +++++++++++++++++++
15 files changed, 339 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i16-m1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i16-m2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i16-m4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i16-mf2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i16-mf4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i32-m1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i32-m2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i32-m4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i32-mf2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-m1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-m2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-m4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-mf2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-mf4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-mf8.c
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i16-m1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i16-m1.c
new file mode 100644
index 00000000000..50fce594ee4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i16-m1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e16m1,
+ vuint16m1_t,
+ vuint32m2_t,
+ __riscv_vle16_v_u16m1,
+ __riscv_vwcvtu_x_x_v_u32m2,
+ __riscv_vse32_v_u32m2,
+ vwcvtu,
+ LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-times {vwcvtu\.x\.x\.v\s+v0,v1([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwcvtu\.x\.x\.v\s+v2,v3([^0-9]|$)} 1 } }
*/
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i16-m2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i16-m2.c
new file mode 100644
index 00000000000..517bfafead8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i16-m2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e16m2,
+ vuint16m2_t,
+ vuint32m4_t,
+ __riscv_vle16_v_u16m2,
+ __riscv_vwcvtu_x_x_v_u32m4,
+ __riscv_vse32_v_u32m4,
+ vwcvtu,
+ LOOP_UNARY_BODY_X8)
+
+/* { dg-final { scan-assembler-times {vwcvtu\.x\.x\.v\s+v0,v2([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwcvtu\.x\.x\.v\s+v4,v6} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i16-m4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i16-m4.c
new file mode 100644
index 00000000000..6d89c23535c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i16-m4.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e16m4,
+ vuint16m4_t,
+ vuint32m8_t,
+ __riscv_vle16_v_u16m4,
+ __riscv_vwcvtu_x_x_v_u32m8,
+ __riscv_vse32_v_u32m8,
+ vwcvtu,
+ LOOP_UNARY_BODY_X4)
+
+/* { dg-final { scan-assembler-times {vwcvtu\.x\.x\.v\s+v0,v4} 1 } } */
+/* { dg-final { scan-assembler-times {vwcvtu\.x\.x\.v\s+v8,v12} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i16-mf2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i16-mf2.c
new file mode 100644
index 00000000000..dad29cfe135
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i16-mf2.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e16m1,
+ vuint16mf2_t,
+ vuint32m1_t,
+ __riscv_vle16_v_u16mf2,
+ __riscv_vwcvtu_x_x_v_u32m1,
+ __riscv_vse32_v_u32m1,
+ vwcvtu,
+ LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v0,v1([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v2,v3([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v4,v5} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v6,v7} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v8,v9} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v10,v11} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v12,v13} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v14,v15} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v16,v17} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v18,v19} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v20,v21} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v22,v23} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v24,v25} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v26,v27} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v28,v29} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v30,v31} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i16-mf4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i16-mf4.c
new file mode 100644
index 00000000000..66a74e7f7d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i16-mf4.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e16m1,
+ vuint16mf4_t,
+ vuint32mf2_t,
+ __riscv_vle16_v_u16mf4,
+ __riscv_vwcvtu_x_x_v_u32mf2,
+ __riscv_vse32_v_u32mf2,
+ vwcvtu,
+ LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v0,v1([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v2,v3([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v4,v5} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v6,v7} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v8,v9} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v10,v11} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v12,v13} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v14,v15} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v16,v17} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v18,v19} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v20,v21} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v22,v23} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v24,v25} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v26,v27} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v28,v29} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v30,v31} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i32-m1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i32-m1.c
new file mode 100644
index 00000000000..041c0a27f0b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i32-m1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e32m1,
+ vuint32m1_t,
+ vuint64m2_t,
+ __riscv_vle32_v_u32m1,
+ __riscv_vwcvtu_x_x_v_u64m2,
+ __riscv_vse64_v_u64m2,
+ vwcvtu,
+ LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-times {vwcvtu\.x\.x\.v\s+v0,v1([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwcvtu\.x\.x\.v\s+v2,v3([^0-9]|$)} 1 } }
*/
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i32-m2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i32-m2.c
new file mode 100644
index 00000000000..cf9664269b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i32-m2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e32m2,
+ vuint32m2_t,
+ vuint64m4_t,
+ __riscv_vle32_v_u32m2,
+ __riscv_vwcvtu_x_x_v_u64m4,
+ __riscv_vse64_v_u64m4,
+ vwcvtu,
+ LOOP_UNARY_BODY_X8)
+
+/* { dg-final { scan-assembler-times {vwcvtu\.x\.x\.v\s+v0,v2([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwcvtu\.x\.x\.v\s+v4,v6} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i32-m4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i32-m4.c
new file mode 100644
index 00000000000..dcdea365e7a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i32-m4.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e32m4,
+ vuint32m4_t,
+ vuint64m8_t,
+ __riscv_vle32_v_u32m4,
+ __riscv_vwcvtu_x_x_v_u64m8,
+ __riscv_vse64_v_u64m8,
+ vwcvtu,
+ LOOP_UNARY_BODY_X4)
+
+/* { dg-final { scan-assembler-times {vwcvtu\.x\.x\.v\s+v0,v4} 1 } } */
+/* { dg-final { scan-assembler-times {vwcvtu\.x\.x\.v\s+v8,v12} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i32-mf2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i32-mf2.c
new file mode 100644
index 00000000000..6546ec37112
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i32-mf2.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e32m1,
+ vuint32mf2_t,
+ vuint64m1_t,
+ __riscv_vle32_v_u32mf2,
+ __riscv_vwcvtu_x_x_v_u64m1,
+ __riscv_vse64_v_u64m1,
+ vwcvtu,
+ LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v0,v1([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v2,v3([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v4,v5} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v6,v7} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v8,v9} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v10,v11} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v12,v13} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v14,v15} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v16,v17} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v18,v19} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v20,v21} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v22,v23} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v24,v25} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v26,v27} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v28,v29} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v30,v31} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-m1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-m1.c
new file mode 100644
index 00000000000..cf93a0ff595
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-m1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e8m1,
+ vuint8m1_t,
+ vuint16m2_t,
+ __riscv_vle8_v_u8m1,
+ __riscv_vwcvtu_x_x_v_u16m2,
+ __riscv_vse16_v_u16m2,
+ vwcvtu,
+ LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-times {vwcvtu\.x\.x\.v\s+v0,v1([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwcvtu\.x\.x\.v\s+v2,v3([^0-9]|$)} 1 } }
*/
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-m2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-m2.c
new file mode 100644
index 00000000000..366b89841d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-m2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e8m2,
+ vuint8m2_t,
+ vuint16m4_t,
+ __riscv_vle8_v_u8m2,
+ __riscv_vwcvtu_x_x_v_u16m4,
+ __riscv_vse16_v_u16m4,
+ vwcvtu,
+ LOOP_UNARY_BODY_X8)
+
+/* { dg-final { scan-assembler-times {vwcvtu\.x\.x\.v\s+v0,v2([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwcvtu\.x\.x\.v\s+v4,v6} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-m4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-m4.c
new file mode 100644
index 00000000000..d64b36dd532
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-m4.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e8m4,
+ vuint8m4_t,
+ vuint16m8_t,
+ __riscv_vle8_v_u8m4,
+ __riscv_vwcvtu_x_x_v_u16m8,
+ __riscv_vse16_v_u16m8,
+ vwcvtu,
+ LOOP_UNARY_BODY_X4)
+
+/* { dg-final { scan-assembler-times {vwcvtu\.x\.x\.v\s+v0,v4} 1 } } */
+/* { dg-final { scan-assembler-times {vwcvtu\.x\.x\.v\s+v8,v12} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-mf2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-mf2.c
new file mode 100644
index 00000000000..bd1cf19cf85
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-mf2.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e8m1,
+ vuint8mf2_t,
+ vuint16m1_t,
+ __riscv_vle8_v_u8mf2,
+ __riscv_vwcvtu_x_x_v_u16m1,
+ __riscv_vse16_v_u16m1,
+ vwcvtu,
+ LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v0,v1([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v2,v3([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v4,v5} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v6,v7} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v8,v9} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v10,v11} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v12,v13} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v14,v15} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v16,v17} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v18,v19} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v20,v21} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v22,v23} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v24,v25} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v26,v27} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v28,v29} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v30,v31} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-mf4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-mf4.c
new file mode 100644
index 00000000000..49eb92ed5f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-mf4.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e8m1,
+ vuint8mf4_t,
+ vuint16mf2_t,
+ __riscv_vle8_v_u8mf4,
+ __riscv_vwcvtu_x_x_v_u16mf2,
+ __riscv_vse16_v_u16mf2,
+ vwcvtu,
+ LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v0,v1([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v2,v3([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v4,v5} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v6,v7} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v8,v9} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v10,v11} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v12,v13} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v14,v15} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v16,v17} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v18,v19} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v20,v21} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v22,v23} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v24,v25} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v26,v27} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v28,v29} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v30,v31} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-mf8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-mf8.c
new file mode 100644
index 00000000000..62e6e887d3e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwcvtu-i8-mf8.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e8m1,
+ vuint8mf8_t,
+ vuint16mf4_t,
+ __riscv_vle8_v_u8mf8,
+ __riscv_vwcvtu_x_x_v_u16mf4,
+ __riscv_vse16_v_u16mf4,
+ vwcvtu,
+ LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v0,v1([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v2,v3([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v4,v5} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v6,v7} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v8,v9} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v10,v11} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v12,v13} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v14,v15} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v16,v17} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v18,v19} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v20,v21} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v22,v23} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v24,v25} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v26,v27} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v28,v29} } } */
+/* { dg-final { scan-assembler-not {vwcvtu\.x\.x\.v\s+v30,v31} } } */
--
2.43.0
