gcc/ChangeLog:
* config/i386/avx10v2auxintrin.h (_mm_cvtbf8_bf4s): New intrins.
(_mm256_cvtbf8_bf4s): Ditto.
(_mm512_cvtbf8_bf4s): Ditto.
(_mm_cvtbf8_bf4s_storeu): Ditto.
(_mm256_cvtbf8_bf4s_storeu): Ditto.
(_mm512_cvtbf8_bf4s_storeu): Ditto.
(_mm_cvthf8_bf4s): Ditto.
(_mm256_cvthf8_bf4s): Ditto.
(_mm512_cvthf8_bf4s): Ditto.
(_mm_cvthf8_bf4s_storeu): Ditto.
(_mm256_cvthf8_bf4s_storeu): Ditto.
(_mm512_cvthf8_bf4s_storeu): Ditto.
(_mm_cvtbf4_hf8): Ditto.
(_mm_mask_cvtbf4_hf8): Ditto.
(_mm_maskz_cvtbf4_hf8): Ditto.
(_mm256_cvtbf4_hf8): Ditto.
(_mm256_mask_cvtbf4_hf8): Ditto.
(_mm256_maskz_cvtbf4_hf8): Ditto.
(_mm512_cvtbf4_hf8): Ditto.
(_mm512_mask_cvtbf4_hf8): Ditto.
(_mm512_maskz_cvtbf4_hf8): Ditto.
* config/i386/i386-builtin-types.def : New function types.
* config/i386/i386-builtin.def (BDESC): Add builtins.
* config/i386/i386-expand.cc (ix86_expand_args_builtin): Handle new
function types.
(ix86_expand_special_args_builtin): Ditto.
* config/i386/sse.md (vcvt<convertfp82bf4>v16qi): New.
(*vcvt<convertfp82bf4>v16qi): Ditto.
(vcvt<convertfp82bf4><mode>): Ditto.
(vcvt<convertfp82bf4><mode>_store): Ditto.
(vcvtbf42hf8<mode><mask_name>): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx10v2aux-convert-1e.c: New test.
* gcc.target/i386/avx10v2aux-convert-1f.c: New test.
Co-authored-by: Venkataramanan Kumar <[email protected]>
Co-authored-by: Haochen Jiang <[email protected]>
---
gcc/config/i386/avx10v2auxintrin.h | 181 ++++++++++++++++++
gcc/config/i386/i386-builtin-types.def | 7 +
gcc/config/i386/i386-builtin.def | 17 ++
gcc/config/i386/i386-expand.cc | 6 +
gcc/config/i386/sse.md | 86 +++++++++
.../gcc.target/i386/avx10v2aux-convert-1e.c | 52 +++++
.../gcc.target/i386/avx10v2aux-convert-1f.c | 36 ++++
7 files changed, 385 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1e.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1f.c
diff --git a/gcc/config/i386/avx10v2auxintrin.h
b/gcc/config/i386/avx10v2auxintrin.h
index a862f3173eb..bc004a24dfb 100644
--- a/gcc/config/i386/avx10v2auxintrin.h
+++ b/gcc/config/i386/avx10v2auxintrin.h
@@ -1195,6 +1195,187 @@ _mm512_maskz_cvthf8_ps (__mmask16 __U, __m128i __A)
(__mmask16) __U);
}
+// VCVTBF82BF4S
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvtbf8_bf4s (__m128i __A)
+{
+ return (__m128i) __builtin_ia32_vcvtbf82bf4s128 ((__v16qi) __A);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvtbf8_bf4s (__m256i __A)
+{
+ return (__m128i) __builtin_ia32_vcvtbf82bf4s256 ((__v32qi) __A);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvtbf8_bf4s (__m512i __A)
+{
+ return (__m256i) __builtin_ia32_vcvtbf82bf4s512 ((__v64qi) __A);
+}
+
+extern __inline void
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvtbf8_bf4s_storeu (void * __P, __m128i __A)
+{
+ __builtin_ia32_vcvtbf82bf4s128mem ((__v8qi *) __P, (__v16qi) __A);
+}
+
+extern __inline void
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvtbf8_bf4s_storeu (void * __P, __m256i __A)
+{
+ __builtin_ia32_vcvtbf82bf4s256mem ((__v16qi *) __P, (__v32qi) __A);
+}
+
+extern __inline void
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvtbf8_bf4s_storeu (void * __P, __m512i __A)
+{
+ __builtin_ia32_vcvtbf82bf4s512mem ((__v32qi *) __P, (__v64qi) __A);
+}
+
+// VCVTHF82BF4S
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvthf8_bf4s (__m128i __A)
+{
+ return (__m128i) __builtin_ia32_vcvthf82bf4s128 ((__v16qi) __A);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvthf8_bf4s (__m256i __A)
+{
+ return (__m128i) __builtin_ia32_vcvthf82bf4s256 ((__v32qi) __A);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvthf8_bf4s (__m512i __A)
+{
+ return (__m256i) __builtin_ia32_vcvthf82bf4s512 ((__v64qi) __A);
+}
+
+extern __inline void
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvthf8_bf4s_storeu (void * __P, __m128i __A)
+{
+ __builtin_ia32_vcvthf82bf4s128mem ((__v8qi *) __P, (__v16qi) __A);
+}
+
+extern __inline void
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvthf8_bf4s_storeu (void * __P, __m256i __A)
+{
+ __builtin_ia32_vcvthf82bf4s256mem ((__v16qi *) __P, (__v32qi) __A);
+}
+
+extern __inline void
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvthf8_bf4s_storeu (void * __P, __m512i __A)
+{
+ __builtin_ia32_vcvthf82bf4s512mem ((__v32qi *) __P, (__v64qi) __A);
+}
+
+// VCVTBF42HF8 - 128-bit
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvtbf4_hf8 (__m128i __A)
+{
+ return (__m128i) __builtin_ia32_vcvtbf42hf8128_mask ((__v16qi) __A,
+ (__v16qi)
+ _mm_undefined_si128 (),
+ (__mmask16) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_cvtbf4_hf8 (__m128i __W, __mmask16 __U, __m128i __A)
+{
+ return (__m128i) __builtin_ia32_vcvtbf42hf8128_mask ((__v16qi) __A,
+ (__v16qi) __W,
+ (__mmask16) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_cvtbf4_hf8 (__mmask16 __U, __m128i __A)
+{
+ return (__m128i) __builtin_ia32_vcvtbf42hf8128_mask ((__v16qi) __A,
+ (__v16qi)
+ _mm_setzero_si128 (),
+ (__mmask16) __U);
+}
+
+// VCVTBF42HF8 - 256-bit
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvtbf4_hf8 (__m128i __A)
+{
+ return (__m256i) __builtin_ia32_vcvtbf42hf8256_mask ((__v16qi) __A,
+ (__v32qi)
+ _mm256_undefined_si256
(),
+ (__mmask32) -1);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvtbf4_hf8 (__m256i __W, __mmask32 __U, __m128i __A)
+{
+ return (__m256i) __builtin_ia32_vcvtbf42hf8256_mask ((__v16qi) __A,
+ (__v32qi) __W,
+ (__mmask32) __U);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvtbf4_hf8 (__mmask32 __U, __m128i __A)
+{
+ return (__m256i) __builtin_ia32_vcvtbf42hf8256_mask ((__v16qi) __A,
+ (__v32qi)
+ _mm256_setzero_si256 (),
+ (__mmask32) __U);
+}
+
+// VCVTBF42HF8 - 512-bit
+
+extern __inline __m512i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvtbf4_hf8 (__m256i __A)
+{
+ return (__m512i) __builtin_ia32_vcvtbf42hf8512_mask ((__v32qi) __A,
+ (__v64qi)
+ _mm512_undefined_si512
(),
+ (__mmask64) -1);
+}
+
+extern __inline __m512i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_cvtbf4_hf8 (__m512i __W, __mmask64 __U, __m256i __A)
+{
+ return (__m512i) __builtin_ia32_vcvtbf42hf8512_mask ((__v32qi) __A,
+ (__v64qi) __W,
+ (__mmask64) __U);
+}
+
+extern __inline __m512i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_maskz_cvtbf4_hf8 (__mmask64 __U, __m256i __A)
+{
+ return (__m512i) __builtin_ia32_vcvtbf42hf8512_mask ((__v32qi) __A,
+ (__v64qi)
+ _mm512_setzero_si512 (),
+ (__mmask64) __U);
+}
+
#ifdef __DISABLE_AVX10V2AUX__
#undef __DISABLE_AVX10V2AUX__
#pragma GCC pop_options
diff --git a/gcc/config/i386/i386-builtin-types.def
b/gcc/config/i386/i386-builtin-types.def
index 20078ba295e..bc72594a124 100644
--- a/gcc/config/i386/i386-builtin-types.def
+++ b/gcc/config/i386/i386-builtin-types.def
@@ -1484,6 +1484,13 @@ DEF_FUNCTION_TYPE (V16QI, V16SI, V16SF, V16QI, UHI)
DEF_FUNCTION_TYPE (V4SF, V16QI, V4SF, UQI)
DEF_FUNCTION_TYPE (V8SF, V16QI, V8SF, UQI)
DEF_FUNCTION_TYPE (V16SF, V16QI, V16SF, UHI)
+DEF_FUNCTION_TYPE (V16QI, V32QI)
+DEF_FUNCTION_TYPE (V32QI, V64QI)
+DEF_FUNCTION_TYPE (V64QI, V32QI, V64QI, UDI)
+DEF_FUNCTION_TYPE (VOID, PV8QI, V16QI)
+DEF_FUNCTION_TYPE (VOID, PV16QI, V32QI)
+DEF_FUNCTION_TYPE (VOID, PV32QI, V64QI)
+
# SM4 builtins
DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI)
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index 07a80e28598..077565d3139 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -523,6 +523,14 @@ BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS |
OPTION_MASK_ISA2_AVX10_2,
BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS |
OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vmovrsqv2di_mask,
"__builtin_ia32_vmovrsq128_mask", IX86_BUILTIN_VMOVRSQ_128, UNKNOWN, (int)
V2DI_FTYPE_PCV2DI_V2DI_UQI)
BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS |
OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vmovrswv8hi_mask,
"__builtin_ia32_vmovrsw128_mask", IX86_BUILTIN_VMOVRSW_128, UNKNOWN, (int)
V8HI_FTYPE_PCV8HI_V8HI_UQI)
+/* AVX10V2AUX. */
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbf82bf4sv16qi_store,
"__builtin_ia32_vcvtbf82bf4s128mem", IX86_BUILTIN_VCVTBF82BF4S128_MEM, UNKNOWN,
(int) VOID_FTYPE_PV8QI_V16QI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbf82bf4sv32qi_store,
"__builtin_ia32_vcvtbf82bf4s256mem", IX86_BUILTIN_VCVTBF82BF4S256_MEM, UNKNOWN,
(int) VOID_FTYPE_PV16QI_V32QI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbf82bf4sv64qi_store,
"__builtin_ia32_vcvtbf82bf4s512mem", IX86_BUILTIN_VCVTBF82BF4S512_MEM, UNKNOWN,
(int) VOID_FTYPE_PV32QI_V64QI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvthf82bf4sv16qi_store,
"__builtin_ia32_vcvthf82bf4s128mem", IX86_BUILTIN_VCVTHF82BF4S128_MEM, UNKNOWN,
(int) VOID_FTYPE_PV8QI_V16QI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvthf82bf4sv32qi_store,
"__builtin_ia32_vcvthf82bf4s256mem", IX86_BUILTIN_VCVTHF82BF4S256_MEM, UNKNOWN,
(int) VOID_FTYPE_PV16QI_V32QI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvthf82bf4sv64qi_store,
"__builtin_ia32_vcvthf82bf4s512mem", IX86_BUILTIN_VCVTHF82BF4S512_MEM, UNKNOWN,
(int) VOID_FTYPE_PV32QI_V64QI)
+
BDESC_END (SPECIAL_ARGS, PURE_ARGS)
/* AVX */
@@ -3406,6 +3414,15 @@ BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX,
CODE_FOR_vcvtbf82psv16sf_mask, "__builtin
BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvthf82psv4sf_mask,
"__builtin_ia32_vcvthf82ps128_mask", IX86_BUILTIN_VCVTHF82PS128_MASK, UNKNOWN,
(int) V4SF_FTYPE_V16QI_V4SF_UQI)
BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvthf82psv8sf_mask,
"__builtin_ia32_vcvthf82ps256_mask", IX86_BUILTIN_VCVTHF82PS256_MASK, UNKNOWN,
(int) V8SF_FTYPE_V16QI_V8SF_UQI)
BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvthf82psv16sf_mask,
"__builtin_ia32_vcvthf82ps512_mask", IX86_BUILTIN_VCVTHF82PS512_MASK, UNKNOWN,
(int) V16SF_FTYPE_V16QI_V16SF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbf82bf4sv16qi,
"__builtin_ia32_vcvtbf82bf4s128", IX86_BUILTIN_VCVTBF82BF4S128, UNKNOWN, (int)
V16QI_FTYPE_V16QI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbf82bf4sv32qi,
"__builtin_ia32_vcvtbf82bf4s256", IX86_BUILTIN_VCVTBF82BF4S256, UNKNOWN, (int)
V16QI_FTYPE_V32QI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbf82bf4sv64qi,
"__builtin_ia32_vcvtbf82bf4s512", IX86_BUILTIN_VCVTBF82BF4S512, UNKNOWN, (int)
V32QI_FTYPE_V64QI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvthf82bf4sv16qi,
"__builtin_ia32_vcvthf82bf4s128", IX86_BUILTIN_VCVTHF82BF4S128, UNKNOWN, (int)
V16QI_FTYPE_V16QI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvthf82bf4sv32qi,
"__builtin_ia32_vcvthf82bf4s256", IX86_BUILTIN_VCVTHF82BF4S256, UNKNOWN, (int)
V16QI_FTYPE_V32QI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvthf82bf4sv64qi,
"__builtin_ia32_vcvthf82bf4s512", IX86_BUILTIN_VCVTHF82BF4S512, UNKNOWN, (int)
V32QI_FTYPE_V64QI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbf42hf8v16qi_mask,
"__builtin_ia32_vcvtbf42hf8128_mask", IX86_BUILTIN_VCVTBF42HF8128_MASK,
UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbf42hf8v32qi_mask,
"__builtin_ia32_vcvtbf42hf8256_mask", IX86_BUILTIN_VCVTBF42HF8256_MASK,
UNKNOWN, (int) V32QI_FTYPE_V16QI_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbf42hf8v64qi_mask,
"__builtin_ia32_vcvtbf42hf8512_mask", IX86_BUILTIN_VCVTBF42HF8512_MASK,
UNKNOWN, (int) V64QI_FTYPE_V32QI_V64QI_UDI)
/* Builtins with rounding support. */
BDESC_END (ARGS, ROUND_ARGS)
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index 511ab7e5733..aea2ac7b31a 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -12684,6 +12684,8 @@ ix86_expand_args_builtin (const struct
builtin_description *d,
case V16BF_FTYPE_V16SF:
case V8BF_FTYPE_V8SF:
case V8BF_FTYPE_V4SF:
+ case V16QI_FTYPE_V32QI:
+ case V32QI_FTYPE_V64QI:
nargs = 1;
break;
case V4SF_FTYPE_V4SF_VEC_MERGE:
@@ -13064,6 +13066,7 @@ ix86_expand_args_builtin (const struct
builtin_description *d,
case V4SF_FTYPE_V16QI_V4SF_UQI:
case V8SF_FTYPE_V16QI_V8SF_UQI:
case V16SF_FTYPE_V16QI_V16SF_UHI:
+ case V64QI_FTYPE_V32QI_V64QI_UDI:
nargs = 3;
break;
case V32QI_FTYPE_V32QI_V32QI_INT:
@@ -14324,6 +14327,9 @@ ix86_expand_special_args_builtin (const struct
builtin_description *d,
case VOID_FTYPE_PV8DI_V8DI:
case VOID_FTYPE_PV4DI_V4DI:
case VOID_FTYPE_PV2DI_V2DI:
+ case VOID_FTYPE_PV8QI_V16QI:
+ case VOID_FTYPE_PV16QI_V32QI:
+ case VOID_FTYPE_PV32QI_V64QI:
case VOID_FTYPE_PCHAR_V32QI:
case VOID_FTYPE_PCHAR_V16QI:
case VOID_FTYPE_PFLOAT_V16SF:
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 1583c59db3b..dd6393cabf9 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -272,6 +272,9 @@
UNSPEC_VCVTBIASPS2HF8S
UNSPEC_VCVTBF82PS
UNSPEC_VCVTHF82PS
+ UNSPEC_VCVTBF82BF4S
+ UNSPEC_VCVTHF82BF4S
+ UNSPEC_VCVTBF42HF8
])
(define_c_enum "unspecv" [
@@ -34380,3 +34383,86 @@
"TARGET_AVX10V2AUX"
"vcvt<convertfp82ps>\t{%1,
%0<mask_operand2>|%0<mask_operand2>,%<iptrssebvec_3>1}"
[(set_attr "prefix" "evex")])
+
+;; FP8 to FP4 converts (VCVTBF82BF4S, VCVTHF82BF4S) - no masking
+
+(define_int_iterator UNSPEC_CONVERTFP82BF4
+ [UNSPEC_VCVTBF82BF4S UNSPEC_VCVTHF82BF4S])
+
+(define_int_attr convertfp82bf4
+ [(UNSPEC_VCVTBF82BF4S "bf82bf4s")
+ (UNSPEC_VCVTHF82BF4S "hf82bf4s")])
+
+(define_mode_iterator FP82FP4_PART [V32QI V64QI])
+
+(define_mode_attr fp82fp4_dest
+ [(V32QI "V16QI") (V64QI "V32QI")])
+
+(define_mode_iterator FP82FP4_MEM [V16QI V32QI V64QI])
+
+(define_mode_attr fp82fp4_mem
+ [(V16QI "V8QI") (V32QI "V16QI") (V64QI "V32QI")])
+
+(define_expand "vcvt<convertfp82bf4>v16qi"
+ [(set (match_operand:V16QI 0 "register_operand")
+ (vec_concat:V16QI
+ (unspec:V8QI
+ [(match_operand:V16QI 1 "register_operand")]
+ UNSPEC_CONVERTFP82BF4)
+ (match_dup 2)))]
+ "TARGET_AVX10V2AUX"
+ "operands[2] = CONST0_RTX (V8QImode);")
+
+(define_insn "*vcvt<convertfp82bf4>v16qi"
+ [(set (match_operand:V16QI 0 "register_operand" "=v")
+ (vec_concat:V16QI
+ (unspec:V8QI
+ [(match_operand:V16QI 1 "register_operand" "v")]
+ UNSPEC_CONVERTFP82BF4)
+ (match_operand:V8QI 2 "const0_operand")))]
+ "TARGET_AVX10V2AUX"
+ "vcvt<convertfp82bf4>\t{%1, %0|%0, %1}"
+ [(set_attr "prefix" "evex")
+ (set_attr "mode" "TI")])
+
+(define_insn "vcvt<convertfp82bf4><mode>"
+ [(set (match_operand:<fp82fp4_dest> 0 "register_operand" "=v")
+ (unspec:<fp82fp4_dest>
+ [(match_operand:FP82FP4_PART 1 "register_operand" "v")]
+ UNSPEC_CONVERTFP82BF4))]
+ "TARGET_AVX10V2AUX"
+ "vcvt<convertfp82bf4>\t{%1, %0|%0, %1}"
+ [(set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
+
+(define_insn "vcvt<convertfp82bf4><mode>_store"
+ [(set (match_operand:<fp82fp4_mem> 0 "memory_operand" "=m")
+ (unspec:<fp82fp4_mem>
+ [(match_operand:FP82FP4_MEM 1 "register_operand" "v")]
+ UNSPEC_CONVERTFP82BF4))]
+ "TARGET_AVX10V2AUX"
+ "vcvt<convertfp82bf4>\t{%1, %0|%0, %1}"
+ [(set_attr "type" "ssecvt")
+ (set_attr "memory" "store")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
+
+;; FP4 to FP8 converts (VCVTBF42HF8) with masking
+
+(define_mode_iterator FP42FP8_MODE [V16QI V32QI V64QI])
+
+(define_mode_attr fp82fp4_src
+ [(V16QI "V16QI") (V32QI "V16QI") (V64QI "V32QI")])
+
+(define_mode_attr iptr_fp42fp8
+ [(V16QI "q") (V32QI "") (V64QI "")])
+
+(define_insn "vcvtbf42hf8<mode><mask_name>"
+ [(set (match_operand:FP42FP8_MODE 0 "register_operand" "=v")
+ (unspec:FP42FP8_MODE
+ [(match_operand:<fp82fp4_src> 1 "nonimmediate_operand" "vm")]
+ UNSPEC_VCVTBF42HF8))]
+ "TARGET_AVX10V2AUX"
+ "vcvtbf42hf8\t{%1, %0<mask_operand2>|%0<mask_operand2>, %<iptr_fp42fp8>1}"
+ [(set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
diff --git a/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1e.c
b/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1e.c
new file mode 100644
index 00000000000..d1faab9899f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1e.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx10v2aux -O2 -fno-fuse-ops-with-volatile-access" } */
+/* { dg-final { scan-assembler-times "vcvtbf82bf4s\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf82bf4s\[
\\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf82bf4s\[
\\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf82bf4s\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf82bf4s\[
\\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf82bf4s\[
\\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf82bf4s\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*\\(%\[a-z0-9\]+\\)(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf82bf4s\[
\\t\]*%ymm\[0-9\]+,\[^\{\n\]*\\(%\[a-z0-9\]+\\)(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf82bf4s\[
\\t\]*%zmm\[0-9\]+,\[^\{\n\]*\\(%\[a-z0-9\]+\\)(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf82bf4s\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*\\(%\[a-z0-9\]+\\)(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf82bf4s\[
\\t\]*%ymm\[0-9\]+,\[^\{\n\]*\\(%\[a-z0-9\]+\\)(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf82bf4s\[
\\t\]*%zmm\[0-9\]+,\[^\{\n\]*\\(%\[a-z0-9\]+\\)(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128i x128i;
+volatile __m256i x256i;
+volatile __m512i x512i;
+
+void extern
+avx10v2aux_vcvtbf82bf4s_test (void)
+{
+ x128i = _mm_cvtbf8_bf4s (x128i);
+ x128i = _mm256_cvtbf8_bf4s (x256i);
+ x256i = _mm512_cvtbf8_bf4s (x512i);
+}
+
+void extern
+avx10v2aux_vcvthf82bf4s_test (void)
+{
+ x128i = _mm_cvthf8_bf4s (x128i);
+ x128i = _mm256_cvthf8_bf4s (x256i);
+ x256i = _mm512_cvthf8_bf4s (x512i);
+}
+
+void extern
+avx10v2aux_vcvtbf82bf4s_store_test (void *p)
+{
+ _mm_cvtbf8_bf4s_storeu (p, x128i);
+ _mm256_cvtbf8_bf4s_storeu (p, x256i);
+ _mm512_cvtbf8_bf4s_storeu (p, x512i);
+}
+
+void extern
+avx10v2aux_vcvthf82bf4s_store_test (void *p)
+{
+ _mm_cvthf8_bf4s_storeu (p, x128i);
+ _mm256_cvthf8_bf4s_storeu (p, x256i);
+ _mm512_cvthf8_bf4s_storeu (p, x512i);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1f.c
b/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1f.c
new file mode 100644
index 00000000000..afed68f8ec6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1f.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx10v2aux -O2 -fno-fuse-ops-with-volatile-access" } */
+/* { dg-final { scan-assembler-times "vcvtbf42hf8\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf42hf8\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvtbf42hf8\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+/* { dg-final { scan-assembler-times "vcvtbf42hf8\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf42hf8\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvtbf42hf8\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+/* { dg-final { scan-assembler-times "vcvtbf42hf8\[
\\t\]*%ymm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf42hf8\[
\\t\]*%ymm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvtbf42hf8\[
\\t\]*%ymm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+
+#include <immintrin.h>
+
+volatile __m128i x128i;
+volatile __m256i x256i;
+volatile __m512i x512i;
+volatile __mmask16 m16;
+volatile __mmask32 m32;
+volatile __mmask64 m64;
+
+void extern
+avx10v2aux_vcvtbf42hf8_test (void)
+{
+ x128i = _mm_cvtbf4_hf8 (x128i);
+ x128i = _mm_mask_cvtbf4_hf8 (x128i, m16, x128i);
+ x128i = _mm_maskz_cvtbf4_hf8 (m16, x128i);
+
+ x256i = _mm256_cvtbf4_hf8 (x128i);
+ x256i = _mm256_mask_cvtbf4_hf8 (x256i, m32, x128i);
+ x256i = _mm256_maskz_cvtbf4_hf8 (m32, x128i);
+
+ x512i = _mm512_cvtbf4_hf8 (x256i);
+ x512i = _mm512_mask_cvtbf4_hf8 (x512i, m64, x256i);
+ x512i = _mm512_maskz_cvtbf4_hf8 (m64, x256i);
+}
--
2.34.1
