> From: Sharma, Dipesh <[email protected]> > Sent: Thursday, July 23, 2026 4:40 PM > > > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index > > > 10850189043..8cf80deb262 100644 > > > --- a/gcc/config/i386/sse.md > > > +++ b/gcc/config/i386/sse.md > > > @@ -34084,3 +34090,129 @@ > > > "vbitrevb\t{%1, %0|%0, %1}" > > > [(set_attr "prefix" "evex") > > > (set_attr "mode" "<sseinsnmode>")]) > > > + > > > +;; AVX10V2AUX instructions > > > +;; FP32 to FP8 single-source converts (VCVTPS2BF8, VCVTPS2BF8S, ;; > > > +VCVTPS2HF8, VCVTPS2HF8S) > > > + > > > +(define_int_iterator UNSPEC_CONVERTPS2FP8 > > > + [UNSPEC_VCVTPS2BF8 UNSPEC_VCVTPS2BF8S > > > + UNSPEC_VCVTPS2HF8 UNSPEC_VCVTPS2HF8S]) > > > + > > > +(define_int_attr convertps2fp8 > > > + [(UNSPEC_VCVTPS2BF8 "ps2bf8") > > > + (UNSPEC_VCVTPS2BF8S "ps2bf8s") > > > + (UNSPEC_VCVTPS2HF8 "ps2hf8") > > > + (UNSPEC_VCVTPS2HF8S "ps2hf8s")]) > > > + > > > +(define_mode_iterator VPS2FP8_PART [V4SF V8SF]) (define_mode_attr > > > +ps2fp8outmode > > > + [(V4SF "V4QI") (V8SF "V8QI")]) > > > +(define_mode_attr ps2fp8padmode > > > + [(V4SF "V12QI") (V8SF "V8QI")]) > > > +(define_mode_attr ps2fp8suff > > > + [(V4SF "{x}") (V8SF "{y}")]) > > > + > > > +(define_expand "vcvt<convertps2fp8><mode>" > > > + [(set (match_operand:V16QI 0 "register_operand") > > > + (vec_concat:V16QI > > > + (unspec:<ps2fp8outmode> > > > + [(match_operand:VPS2FP8_PART 1 "nonimmediate_operand")] > > > + UNSPEC_CONVERTPS2FP8) > > > + (match_dup 2)))] > > > + "TARGET_AVX10V2AUX" > > > + "operands[2] = CONST0_RTX (<ps2fp8padmode>mode);") > > > > I could not say it wrong, but it is hard for others to understand the > > pattern > > from the first glance. It even takes me, who has implemented the inst, a few > > seconds to verify and double check everything is correct. Could you kindly > > split them into two, one for V4SF, the other for V8SF, just like the > > majority of > > previous similar occurrences for down convert and just what you have done > > for mask version? > Since we were using iterators wherever possible, I thought iterating is better > than duplicating the pattern. > Will add separate them if you insist.
Let's see what opinion others have. > > > > > + > > > +(define_insn "*vcvt<convertps2fp8><mode>" > > > + [(set (match_operand:V16QI 0 "register_operand" "=v") > > > + (vec_concat:V16QI > > > + (unspec:<ps2fp8outmode> > > > + [(match_operand:VPS2FP8_PART 1 "nonimmediate_operand" > > > "vm")] > > > > I know we are missing bsct_vector_operand/vmBr for many insts supporting > > broadcast, but let's not introduce more. > Sure we can add. > With the narrower modes where we are manually handling the pattern(v4sf > and v8sf), > Broadcast folding is rejected by combiner with the vec_select pattern for > maskz intrinsics. > Hence we need to add a separate maskz defin_insn to be able to fold it at >-O1 > for v4sf and v8sf. > Let me know your thoughts on it. > > > > > I am trying to work on a patch to fix the legacy missing part, first with > > the help > > of AI to figure out the current gap to estimate the effort. Hope it is not > > too > > huge. > Or instead of adding it now, we can stick to the vm pattern for now and once > your patch lands, we will post a patch to address the bsct_vector_operand > support for these inst. > I suppose let's keep the current implementation as-is. Broadcast gap is much bigger than I thought. Thx, Haochen
