gcc/ChangeLog:
* config/i386/avx10v2auxintrin.h (_mm_cvtbf8_ps): New intrins.
(_mm_mask_cvtbf8_ps): Ditto.
(_mm_maskz_cvtbf8_ps): Ditto.
(_mm256_cvtbf8_ps): Ditto.
(_mm256_mask_cvtbf8_ps): Ditto.
(_mm256_maskz_cvtbf8_ps): Ditto.
(_mm512_cvtbf8_ps): Ditto.
(_mm512_mask_cvtbf8_ps): Ditto.
(_mm512_maskz_cvtbf8_ps): Ditto.
(_mm_cvthf8_ps): Ditto.
(_mm_mask_cvthf8_ps): Ditto.
(_mm_maskz_cvthf8_ps): Ditto.
(_mm256_cvthf8_ps): Ditto.
(_mm256_mask_cvthf8_ps): Ditto.
(_mm256_maskz_cvthf8_ps): Ditto.
(_mm512_cvthf8_ps): Ditto.
(_mm512_mask_cvthf8_ps): Ditto.
(_mm512_maskz_cvthf8_ps): Ditto.
* config/i386/i386-builtin-types.def (V4SF): New function types.
(V8SF): Ditto.
(V16SF): Ditto.
* config/i386/i386-builtin.def (BDESC): New builtins for avx10v2aux.
* config/i386/i386-expand.cc (ix86_expand_args_builtin): Handle new
function types.
* config/i386/sse.md (vcvt<convertfp82ps><mode><mask_name>): New.
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx10v2aux-convert-1d.c: New test.
Co-authored-by: Venkataramanan Kumar <[email protected]>
Co-authored-by: Haochen Jiang <[email protected]>
---
gcc/config/i386/avx10v2auxintrin.h | 187 ++++++++++++++++++
gcc/config/i386/i386-builtin-types.def | 3 +
gcc/config/i386/i386-builtin.def | 6 +
gcc/config/i386/i386-expand.cc | 3 +
gcc/config/i386/sse.md | 28 +++
.../gcc.target/i386/avx10v2aux-convert-1d.c | 61 ++++++
6 files changed, 288 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1d.c
diff --git a/gcc/config/i386/avx10v2auxintrin.h
b/gcc/config/i386/avx10v2auxintrin.h
index d67556352cc..a862f3173eb 100644
--- a/gcc/config/i386/avx10v2auxintrin.h
+++ b/gcc/config/i386/avx10v2auxintrin.h
@@ -1008,6 +1008,193 @@ _mm512_maskz_cvts_biasps_hf8 (__mmask16 __U, __m512i
__A, __m512 __B)
(__mmask16) __U);
}
+// VCVTBF82PS - 128-bit
+
+extern __inline __m128
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvtbf8_ps (__m128i __A)
+{
+ return (__m128) __builtin_ia32_vcvtbf82ps128_mask ((__v16qi) __A,
+ (__v4sf)
+ _mm_undefined_si128 (),
+ (__mmask8) -1);
+}
+
+
+extern __inline __m128
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_cvtbf8_ps (__m128 __W, __mmask8 __U, __m128i __A)
+{
+ return (__m128) __builtin_ia32_vcvtbf82ps128_mask ((__v16qi) __A,
+ (__v4sf) __W,
+ (__mmask8) __U);
+}
+
+extern __inline __m128
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_cvtbf8_ps (__mmask8 __U, __m128i __A)
+{
+ return (__m128) __builtin_ia32_vcvtbf82ps128_mask ((__v16qi) __A,
+ (__v4sf)
+ _mm_setzero_si128 (),
+ (__mmask8) __U);
+}
+
+// VCVTBF82PS - 256-bit
+
+extern __inline __m256
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvtbf8_ps (__m128i __A)
+{
+ return (__m256) __builtin_ia32_vcvtbf82ps256_mask ((__v16qi) __A,
+ (__v8sf)
+ _mm256_undefined_si256 (),
+ (__mmask8) -1);
+}
+
+extern __inline __m256
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvtbf8_ps (__m256 __W, __mmask8 __U, __m128i __A)
+{
+ return (__m256) __builtin_ia32_vcvtbf82ps256_mask ((__v16qi) __A,
+ (__v8sf) __W,
+ (__mmask8) __U);
+}
+
+extern __inline __m256
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvtbf8_ps (__mmask8 __U, __m128i __A)
+{
+ return (__m256) __builtin_ia32_vcvtbf82ps256_mask ((__v16qi) __A,
+ (__v8sf)
+ _mm256_setzero_si256 (),
+ (__mmask8) __U);
+}
+
+// VCVTBF82PS - 512-bit
+
+extern __inline __m512
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvtbf8_ps (__m128i __A)
+{
+ return (__m512) __builtin_ia32_vcvtbf82ps512_mask ((__v16qi) __A,
+ (__v16sf)
+ _mm512_undefined_si512 (),
+ (__mmask16) -1);
+}
+
+extern __inline __m512
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_cvtbf8_ps (__m512 __W, __mmask16 __U, __m128i __A)
+{
+ return (__m512) __builtin_ia32_vcvtbf82ps512_mask ((__v16qi) __A,
+ (__v16sf) __W,
+ (__mmask16) __U);
+}
+
+extern __inline __m512
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_maskz_cvtbf8_ps (__mmask16 __U, __m128i __A)
+{
+ return (__m512) __builtin_ia32_vcvtbf82ps512_mask ((__v16qi) __A,
+ (__v16sf)
+ _mm512_setzero_si512 (),
+ (__mmask16) __U);
+}
+
+// // VCVTHF82PS - 128-bit
+
+extern __inline __m128
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvthf8_ps (__m128i __A)
+{
+ return (__m128) __builtin_ia32_vcvthf82ps128_mask ((__v16qi) __A,
+ (__v4sf)
+ _mm_undefined_si128 (),
+ (__mmask8) -1);
+}
+
+extern __inline __m128
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_cvthf8_ps (__m128 __W, __mmask8 __U, __m128i __A)
+{
+ return (__m128) __builtin_ia32_vcvthf82ps128_mask ((__v16qi) __A,
+ (__v4sf) __W,
+ (__mmask8) __U);
+}
+
+extern __inline __m128
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_cvthf8_ps (__mmask8 __U, __m128i __A)
+{
+ return (__m128) __builtin_ia32_vcvthf82ps128_mask ((__v16qi) __A,
+ (__v4sf)
+ _mm_setzero_si128 (),
+ (__mmask8) __U);
+}
+
+// VCVTHF82PS - 256-bit
+
+extern __inline __m256
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvthf8_ps (__m128i __A)
+{
+ return (__m256) __builtin_ia32_vcvthf82ps256_mask ((__v16qi) __A,
+ (__v8sf)
+ _mm256_undefined_si256 (),
+ (__mmask8) -1);
+}
+
+extern __inline __m256
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvthf8_ps (__m256 __W, __mmask8 __U, __m128i __A)
+{
+ return (__m256) __builtin_ia32_vcvthf82ps256_mask ((__v16qi) __A,
+ (__v8sf) __W,
+ (__mmask8) __U);
+}
+
+extern __inline __m256
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvthf8_ps (__mmask8 __U, __m128i __A)
+{
+ return (__m256) __builtin_ia32_vcvthf82ps256_mask ((__v16qi) __A,
+ (__v8sf)
+ _mm256_setzero_si256 (),
+ (__mmask8) __U);
+}
+
+// VCVTHF82PS - 512-bit
+
+extern __inline __m512
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvthf8_ps (__m128i __A)
+{
+ return (__m512) __builtin_ia32_vcvthf82ps512_mask ((__v16qi) __A,
+ (__v16sf)
+ _mm512_undefined_si512 (),
+ (__mmask16) -1);
+}
+
+extern __inline __m512
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_cvthf8_ps (__m512 __W, __mmask16 __U, __m128i __A)
+{
+ return (__m512) __builtin_ia32_vcvthf82ps512_mask ((__v16qi) __A,
+ (__v16sf) __W,
+ (__mmask16) __U);
+}
+
+extern __inline __m512
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_maskz_cvthf8_ps (__mmask16 __U, __m128i __A)
+{
+ return (__m512) __builtin_ia32_vcvthf82ps512_mask ((__v16qi) __A,
+ (__v16sf)
+ _mm512_setzero_si512 (),
+ (__mmask16) __U);
+}
+
#ifdef __DISABLE_AVX10V2AUX__
#undef __DISABLE_AVX10V2AUX__
#pragma GCC pop_options
diff --git a/gcc/config/i386/i386-builtin-types.def
b/gcc/config/i386/i386-builtin-types.def
index b53219c9aa8..20078ba295e 100644
--- a/gcc/config/i386/i386-builtin-types.def
+++ b/gcc/config/i386/i386-builtin-types.def
@@ -1481,6 +1481,9 @@ DEF_FUNCTION_TYPE (V16QI, V16SF, V16QI, UHI)
DEF_FUNCTION_TYPE (V16QI, V4SI, V4SF, V16QI, UQI)
DEF_FUNCTION_TYPE (V16QI, V8SI, V8SF, V16QI, UQI)
DEF_FUNCTION_TYPE (V16QI, V16SI, V16SF, V16QI, UHI)
+DEF_FUNCTION_TYPE (V4SF, V16QI, V4SF, UQI)
+DEF_FUNCTION_TYPE (V8SF, V16QI, V8SF, UQI)
+DEF_FUNCTION_TYPE (V16SF, V16QI, V16SF, UHI)
# SM4 builtins
DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI)
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index db10e6fe351..07a80e28598 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -3400,6 +3400,12 @@ BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX,
CODE_FOR_vcvtbiasps2hf8v16sf_mask, "__bui
BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbiasps2hf8sv4sf_mask,
"__builtin_ia32_vcvtbiasps2hf8s128_mask", IX86_BUILTIN_VCVTBIASPS2HF8S128_MASK,
UNKNOWN, (int) V16QI_FTYPE_V4SI_V4SF_V16QI_UQI)
BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbiasps2hf8sv8sf_mask,
"__builtin_ia32_vcvtbiasps2hf8s256_mask", IX86_BUILTIN_VCVTBIASPS2HF8S256_MASK,
UNKNOWN, (int) V16QI_FTYPE_V8SI_V8SF_V16QI_UQI)
BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbiasps2hf8sv16sf_mask,
"__builtin_ia32_vcvtbiasps2hf8s512_mask", IX86_BUILTIN_VCVTBIASPS2HF8S512_MASK,
UNKNOWN, (int) V16QI_FTYPE_V16SI_V16SF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbf82psv4sf_mask,
"__builtin_ia32_vcvtbf82ps128_mask", IX86_BUILTIN_VCVTBF82PS128_MASK, UNKNOWN,
(int) V4SF_FTYPE_V16QI_V4SF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbf82psv8sf_mask,
"__builtin_ia32_vcvtbf82ps256_mask", IX86_BUILTIN_VCVTBF82PS256_MASK, UNKNOWN,
(int) V8SF_FTYPE_V16QI_V8SF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbf82psv16sf_mask,
"__builtin_ia32_vcvtbf82ps512_mask", IX86_BUILTIN_VCVTBF82PS512_MASK, UNKNOWN,
(int) V16SF_FTYPE_V16QI_V16SF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvthf82psv4sf_mask,
"__builtin_ia32_vcvthf82ps128_mask", IX86_BUILTIN_VCVTHF82PS128_MASK, UNKNOWN,
(int) V4SF_FTYPE_V16QI_V4SF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvthf82psv8sf_mask,
"__builtin_ia32_vcvthf82ps256_mask", IX86_BUILTIN_VCVTHF82PS256_MASK, UNKNOWN,
(int) V8SF_FTYPE_V16QI_V8SF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvthf82psv16sf_mask,
"__builtin_ia32_vcvthf82ps512_mask", IX86_BUILTIN_VCVTHF82PS512_MASK, UNKNOWN,
(int) V16SF_FTYPE_V16QI_V16SF_UHI)
/* Builtins with rounding support. */
BDESC_END (ARGS, ROUND_ARGS)
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index c85417943b9..511ab7e5733 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -13061,6 +13061,9 @@ ix86_expand_args_builtin (const struct
builtin_description *d,
case V16QI_FTYPE_V4SF_V16QI_UQI:
case V16QI_FTYPE_V8SF_V16QI_UQI:
case V16QI_FTYPE_V16SF_V16QI_UHI:
+ case V4SF_FTYPE_V16QI_V4SF_UQI:
+ case V8SF_FTYPE_V16QI_V8SF_UQI:
+ case V16SF_FTYPE_V16QI_V16SF_UHI:
nargs = 3;
break;
case V32QI_FTYPE_V32QI_V32QI_INT:
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 234acd7aa21..1583c59db3b 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -270,6 +270,8 @@
UNSPEC_VCVTBIASPS2BF8S
UNSPEC_VCVTBIASPS2HF8
UNSPEC_VCVTBIASPS2HF8S
+ UNSPEC_VCVTBF82PS
+ UNSPEC_VCVTHF82PS
])
(define_c_enum "unspecv" [
@@ -34352,3 +34354,29 @@
"vcvt<biasps2fp8>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "prefix" "evex")
(set_attr "mode" "V16SF")])
+
+;; FP8 to FP32 converts (VCVTBF82PS, VCVTHF82PS)
+
+(define_int_iterator UNSPEC_CONVERTFP82PS
+ [UNSPEC_VCVTBF82PS UNSPEC_VCVTHF82PS])
+
+(define_int_attr convertfp82ps
+ [(UNSPEC_VCVTBF82PS "bf82ps")
+ (UNSPEC_VCVTHF82PS "hf82ps")])
+
+(define_mode_iterator FP82PS_MODE [V4SF V8SF V16SF])
+
+(define_mode_attr ssebvecmode_3
+ [(V4SF "V16QI") (V8SF "V16QI") (V16SF "V16QI")])
+
+(define_mode_attr iptrssebvec_3
+ [(V4SF "k") (V8SF "q") (V16SF "")])
+
+(define_insn "vcvt<convertfp82ps><mode><mask_name>"
+ [(set (match_operand:FP82PS_MODE 0 "register_operand" "=v")
+ (unspec:FP82PS_MODE
+ [(match_operand:<ssebvecmode_3> 1 "nonimmediate_operand" "vm")]
+ UNSPEC_CONVERTFP82PS))]
+ "TARGET_AVX10V2AUX"
+ "vcvt<convertfp82ps>\t{%1,
%0<mask_operand2>|%0<mask_operand2>,%<iptrssebvec_3>1}"
+ [(set_attr "prefix" "evex")])
diff --git a/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1d.c
b/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1d.c
new file mode 100644
index 00000000000..a73038b7cc9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1d.c
@@ -0,0 +1,61 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx10v2aux -O2 -fno-fuse-ops-with-volatile-access" } */
+/* { dg-final { scan-assembler-times "vcvtbf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvtbf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+/* { dg-final { scan-assembler-times "vcvtbf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvtbf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+/* { dg-final { scan-assembler-times "vcvtbf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvtbf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+/* { dg-final { scan-assembler-times "vcvthf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvthf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+/* { dg-final { scan-assembler-times "vcvthf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvthf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+/* { dg-final { scan-assembler-times "vcvthf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvthf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+
+#include <immintrin.h>
+
+volatile __m128i x128i;
+volatile __m128 xf128;
+volatile __m256 xf256;
+volatile __m512 xf512;
+volatile __mmask8 m8;
+volatile __mmask16 m16;
+
+void extern
+avx10v2aux_vcvtbf82ps_test (void)
+{
+ xf128 = _mm_cvtbf8_ps (x128i);
+ xf128 = _mm_mask_cvtbf8_ps (xf128, m8, x128i);
+ xf128 = _mm_maskz_cvtbf8_ps (m8, x128i);
+
+ xf256 = _mm256_cvtbf8_ps (x128i);
+ xf256 = _mm256_mask_cvtbf8_ps (xf256, m8, x128i);
+ xf256 = _mm256_maskz_cvtbf8_ps (m8, x128i);
+
+ xf512 = _mm512_cvtbf8_ps (x128i);
+ xf512 = _mm512_mask_cvtbf8_ps (xf512, m16, x128i);
+ xf512 = _mm512_maskz_cvtbf8_ps (m16, x128i);
+}
+
+void extern
+avx10v2aux_vcvthf82ps_test (void)
+{
+ xf128 = _mm_cvthf8_ps (x128i);
+ xf128 = _mm_mask_cvthf8_ps (xf128, m8, x128i);
+ xf128 = _mm_maskz_cvthf8_ps (m8, x128i);
+
+ xf256 = _mm256_cvthf8_ps (x128i);
+ xf256 = _mm256_mask_cvthf8_ps (xf256, m8, x128i);
+ xf256 = _mm256_maskz_cvthf8_ps (m8, x128i);
+
+ xf512 = _mm512_cvthf8_ps (x128i);
+ xf512 = _mm512_mask_cvthf8_ps (xf512, m16, x128i);
+ xf512 = _mm512_maskz_cvthf8_ps (m16, x128i);
+}
--
2.34.1
