> From: Dipesh Sharma <[email protected]>
> Sent: Monday, July 20, 2026 2:24 AM
> diff --git a/gcc/common/config/i386/cpuinfo.h
> b/gcc/common/config/i386/cpuinfo.h
> index 0fe7eb795b0..f4374e9033c 100644
> --- a/gcc/common/config/i386/cpuinfo.h
> +++ b/gcc/common/config/i386/cpuinfo.h
> @@ -1137,6 +1138,13 @@ get_available_features (struct __processor_model
> *cpu_model,
> set_feature (FEATURE_AVX10_1);
> break;
> }
> + if (max_subleaf_level>=1)
> + {
> + /* CPUID.(EAX=24H, ECX=1) for AVX10V2AUX features. */
This line of comment is not accurate. Maybe more other features will use
this. We could simply remove it since it is quite obvious.
> + __cpuid_count (0x24, 1, eax, ebx, ecx, edx);
> + if (ecx & bit_AVX10V2AUX)
> + set_feature (FEATURE_AVX10V2AUX);
> + }
> }
>
> diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
> index 158090c2bde..8518065572f 100644
> --- a/gcc/config/i386/i386.opt
> +++ b/gcc/config/i386/i386.opt
> @@ -1385,3 +1385,7 @@ Support AMX-MOVRS built-in functions and code
> generation.
> mavx512bmm
> Target Mask(ISA2_AVX512BMM) Var(ix86_isa_flags2) Save
> Support AVX512BMM built-in functions and code generation.
> +
> +mavx10v2aux
> +Target Mask(ISA2_AVX10V2AUX) Var(ix86_isa_flags2) Save
> +Support AVX10V2AUX built-in functions and code generation.
Could you also briefly name the ISAs that implies, i.e.,
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
AVX10.1 and AVX10V2AUX built-in functions and code generation.
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index 10850189043..8cf80deb262 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -34084,3 +34090,129 @@
> "vbitrevb\t{%1, %0|%0, %1}"
> [(set_attr "prefix" "evex")
> (set_attr "mode" "<sseinsnmode>")])
> +
> +;; AVX10V2AUX instructions
> +;; FP32 to FP8 single-source converts (VCVTPS2BF8, VCVTPS2BF8S,
> +;; VCVTPS2HF8, VCVTPS2HF8S)
> +
> +(define_int_iterator UNSPEC_CONVERTPS2FP8
> + [UNSPEC_VCVTPS2BF8 UNSPEC_VCVTPS2BF8S
> + UNSPEC_VCVTPS2HF8 UNSPEC_VCVTPS2HF8S])
> +
> +(define_int_attr convertps2fp8
> + [(UNSPEC_VCVTPS2BF8 "ps2bf8")
> + (UNSPEC_VCVTPS2BF8S "ps2bf8s")
> + (UNSPEC_VCVTPS2HF8 "ps2hf8")
> + (UNSPEC_VCVTPS2HF8S "ps2hf8s")])
> +
> +(define_mode_iterator VPS2FP8_PART [V4SF V8SF])
> +(define_mode_attr ps2fp8outmode
> + [(V4SF "V4QI") (V8SF "V8QI")])
> +(define_mode_attr ps2fp8padmode
> + [(V4SF "V12QI") (V8SF "V8QI")])
> +(define_mode_attr ps2fp8suff
> + [(V4SF "{x}") (V8SF "{y}")])
> +
> +(define_expand "vcvt<convertps2fp8><mode>"
> + [(set (match_operand:V16QI 0 "register_operand")
> + (vec_concat:V16QI
> + (unspec:<ps2fp8outmode>
> + [(match_operand:VPS2FP8_PART 1 "nonimmediate_operand")]
> + UNSPEC_CONVERTPS2FP8)
> + (match_dup 2)))]
> + "TARGET_AVX10V2AUX"
> + "operands[2] = CONST0_RTX (<ps2fp8padmode>mode);")
I could not say it wrong, but it is hard for others to understand the pattern
from the first glance. It even takes me, who has implemented the inst, a few
seconds to verify and double check everything is correct. Could you kindly
split them into two, one for V4SF, the other for V8SF, just like the majority
of previous similar occurrences for down convert and just what you have
done for mask version?
> +
> +(define_insn "*vcvt<convertps2fp8><mode>"
> + [(set (match_operand:V16QI 0 "register_operand" "=v")
> + (vec_concat:V16QI
> + (unspec:<ps2fp8outmode>
> + [(match_operand:VPS2FP8_PART 1 "nonimmediate_operand"
> "vm")]
I know we are missing bsct_vector_operand/vmBr for many insts supporting
broadcast, but let's not introduce more.
I am trying to work on a patch to fix the legacy missing part, first with the
help
of AI to figure out the current gap to estimate the effort. Hope it is not too
huge.
> + UNSPEC_CONVERTPS2FP8)
> + (match_operand:<ps2fp8padmode> 2 "const0_operand")))]
> + "TARGET_AVX10V2AUX"
> + "vcvt<convertps2fp8><ps2fp8suff>\t{%1, %0|%0, %1}"
> + [(set_attr "prefix" "evex")
> + (set_attr "mode" "<MODE>")])
> +
> +(define_insn "vcvt<convertps2fp8>v16sf<mask_name>"
> + [(set (match_operand:V16QI 0 "register_operand" "=v")
> + (unspec:V16QI
> + [(match_operand:V16SF 1 "nonimmediate_operand" "vm")]
> + UNSPEC_CONVERTPS2FP8))]
> + "TARGET_AVX10V2AUX"
> +
> "vcvt<convertps2fp8>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %
> 1}"
The {z} suffix is needed here for memory indication since for the other operand,
it is always xmm.
> + [(set_attr "prefix" "evex")
> + (set_attr "mode" "V16SF")])
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index 2c2ed1a003f..b9940d6470b 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -1552,9 +1552,9 @@ See RS/6000 and PowerPC Options.
> -mavxvnni -mamx-fp8 -mavx512fp16 -mavxifma -mavxvnniint8
> -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint
> -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mapxf
> --musermsr -mavx10.1 -mavx10.2 -mamx-avx512 -mmovrs -mamx-movrs
> --mavx512bmm
> --mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops
> +-musermsr -mavx10.1 -mavx10.2 -mamx-avx512 -mmovrs -mamx-movrs
> +-mavx512bmm -mavx10v2aux -mcldemote -mms-bitfields -mno-align-
> stringops
Could you please don't move -mcldemote line to this line?
> +-minline-all-stringops
> -minline-stringops-dynamically -mstringop-strategy=@var{alg}
> -mkl -mwidekl
> -mmemcpy-strategy=@var{strategy} -mmemset-strategy=@var{strategy}
> @@ -36233,6 +36233,11 @@ Support MOVRS built-in functions and code
> generation.
> @opindex mno-amx-movrs
> @item -mamx-movrs
> Support AMX-MOVRS built-in functions and code generation.
> +
> +@opindex mavx10v2aux
> +@opindex mno-avx10v2aux
> +@item -mavx10v2aux
> +Support AVX10V2AUX built-in functions and code generation.
You will also need to add changes similar to i386.opt here.
Thx,
Haochen
