From: Pan Li <[email protected]>
Add test cases for the register group overlap of the vfwsub.wv, to
ensure the narrow operand vs1 will not fall inside the vs2 register
group.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-m1.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-m2.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-m4.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-mf2.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-mf4.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f32-m1.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f32-m2.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f32-m4.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f32-mf2.c: New
test.
Signed-off-by: Pan Li <[email protected]>
---
.../autovec/group_overlap/vfwsub_wv-f16-m1.c | 20 +++++++++++++++++++
.../autovec/group_overlap/vfwsub_wv-f16-m2.c | 20 +++++++++++++++++++
.../autovec/group_overlap/vfwsub_wv-f16-m4.c | 20 +++++++++++++++++++
.../autovec/group_overlap/vfwsub_wv-f16-mf2.c | 19 ++++++++++++++++++
.../autovec/group_overlap/vfwsub_wv-f16-mf4.c | 19 ++++++++++++++++++
.../autovec/group_overlap/vfwsub_wv-f32-m1.c | 20 +++++++++++++++++++
.../autovec/group_overlap/vfwsub_wv-f32-m2.c | 20 +++++++++++++++++++
.../autovec/group_overlap/vfwsub_wv-f32-m4.c | 20 +++++++++++++++++++
.../autovec/group_overlap/vfwsub_wv-f32-mf2.c | 19 ++++++++++++++++++
9 files changed, 177 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-m1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-m2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-m4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-mf2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-mf4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f32-m1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f32-m2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f32-m4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f32-mf2.c
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-m1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-m1.c
new file mode 100644
index 00000000000..1bcfbffb46e
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-m1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_0(
+ __riscv_vsetvlmax_e16m1,
+ vfloat16m1_t,
+ vfloat32m2_t,
+ __riscv_vle16_v_f16m1,
+ __riscv_vle32_v_f32m2,
+ __riscv_vfwsub_wv_f32m2,
+ __riscv_vse32_v_f32m2,
+ vfwsub_wv,
+ LOOP_WIDEN_BINARY_BODY_X16)
+
+/* The narrow source has EMUL == 1, thus the widened destination register
+ group may overlap it in the highest-numbered part. */
+/* { dg-final { scan-assembler-times {vfwsub\.wv\s+v0,v4,v1([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vfwsub\.wv\s+v18,v4,v19([^0-9]|$)} 1 } }
*/
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-m2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-m2.c
new file mode 100644
index 00000000000..3984c535ee9
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-m2.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_0(
+ __riscv_vsetvlmax_e16m2,
+ vfloat16m2_t,
+ vfloat32m4_t,
+ __riscv_vle16_v_f16m2,
+ __riscv_vle32_v_f32m4,
+ __riscv_vfwsub_wv_f32m4,
+ __riscv_vse32_v_f32m4,
+ vfwsub_wv,
+ LOOP_WIDEN_BINARY_BODY_X8)
+
+/* The narrow source has EMUL == 2, thus the widened destination register
+ group may overlap it in the highest-numbered part. */
+/* { dg-final { scan-assembler-times {vfwsub\.wv\s+v0,v8,v2([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vfwsub\.wv\s+v16,v16,v0([^0-9]|$)} 1 } }
*/
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-m4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-m4.c
new file mode 100644
index 00000000000..58083b15b65
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-m4.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_0(
+ __riscv_vsetvlmax_e16m4,
+ vfloat16m4_t,
+ vfloat32m8_t,
+ __riscv_vle16_v_f16m4,
+ __riscv_vle32_v_f32m8,
+ __riscv_vfwsub_wv_f32m8,
+ __riscv_vse32_v_f32m8,
+ vfwsub_wv,
+ LOOP_WIDEN_BINARY_BODY_X4)
+
+/* The narrow source has EMUL == 4, thus the widened destination register
+ group may overlap it in the highest-numbered part. */
+/* { dg-final { scan-assembler-times {vfwsub\.wv\s+v16,v0,v20([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vfwsub\.wv\s+v8,v8,v28([^0-9]|$)} 1 } }
*/
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-mf2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-mf2.c
new file mode 100644
index 00000000000..162223a89eb
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-mf2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_0(
+ __riscv_vsetvlmax_e16m1,
+ vfloat16mf2_t,
+ vfloat32m1_t,
+ __riscv_vle16_v_f16mf2,
+ __riscv_vle32_v_f32m1,
+ __riscv_vfwsub_wv_f32m1,
+ __riscv_vse32_v_f32m1,
+ vfwsub_wv,
+ LOOP_WIDEN_BINARY_BODY_X16)
+
+/* The narrow source has EMUL < 1, thus the widened destination register
+ group must not overlap it at all. */
+/* { dg-final { scan-assembler-not
{vfwsub\.wv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-mf4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-mf4.c
new file mode 100644
index 00000000000..624697ee918
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-mf4.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_0(
+ __riscv_vsetvlmax_e16m1,
+ vfloat16mf4_t,
+ vfloat32mf2_t,
+ __riscv_vle16_v_f16mf4,
+ __riscv_vle32_v_f32mf2,
+ __riscv_vfwsub_wv_f32mf2,
+ __riscv_vse32_v_f32mf2,
+ vfwsub_wv,
+ LOOP_WIDEN_BINARY_BODY_X16)
+
+/* The narrow source has EMUL < 1, thus the widened destination register
+ group must not overlap it at all. */
+/* { dg-final { scan-assembler-not
{vfwsub\.wv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f32-m1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f32-m1.c
new file mode 100644
index 00000000000..4f7987d61be
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f32-m1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_0(
+ __riscv_vsetvlmax_e32m1,
+ vfloat32m1_t,
+ vfloat64m2_t,
+ __riscv_vle32_v_f32m1,
+ __riscv_vle64_v_f64m2,
+ __riscv_vfwsub_wv_f64m2,
+ __riscv_vse64_v_f64m2,
+ vfwsub_wv,
+ LOOP_WIDEN_BINARY_BODY_X16)
+
+/* The narrow source has EMUL == 1, thus the widened destination register
+ group may overlap it in the highest-numbered part. */
+/* { dg-final { scan-assembler-times {vfwsub\.wv\s+v0,v4,v1([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vfwsub\.wv\s+v18,v4,v19([^0-9]|$)} 1 } }
*/
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f32-m2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f32-m2.c
new file mode 100644
index 00000000000..f453595a763
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f32-m2.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_0(
+ __riscv_vsetvlmax_e32m2,
+ vfloat32m2_t,
+ vfloat64m4_t,
+ __riscv_vle32_v_f32m2,
+ __riscv_vle64_v_f64m4,
+ __riscv_vfwsub_wv_f64m4,
+ __riscv_vse64_v_f64m4,
+ vfwsub_wv,
+ LOOP_WIDEN_BINARY_BODY_X8)
+
+/* The narrow source has EMUL == 2, thus the widened destination register
+ group may overlap it in the highest-numbered part. */
+/* { dg-final { scan-assembler-times {vfwsub\.wv\s+v0,v8,v2([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vfwsub\.wv\s+v16,v16,v0([^0-9]|$)} 1 } }
*/
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f32-m4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f32-m4.c
new file mode 100644
index 00000000000..91fc5a1dbf1
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f32-m4.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_0(
+ __riscv_vsetvlmax_e32m4,
+ vfloat32m4_t,
+ vfloat64m8_t,
+ __riscv_vle32_v_f32m4,
+ __riscv_vle64_v_f64m8,
+ __riscv_vfwsub_wv_f64m8,
+ __riscv_vse64_v_f64m8,
+ vfwsub_wv,
+ LOOP_WIDEN_BINARY_BODY_X4)
+
+/* The narrow source has EMUL == 4, thus the widened destination register
+ group may overlap it in the highest-numbered part. */
+/* { dg-final { scan-assembler-times {vfwsub\.wv\s+v16,v0,v20([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vfwsub\.wv\s+v8,v8,v28([^0-9]|$)} 1 } }
*/
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f32-mf2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f32-mf2.c
new file mode 100644
index 00000000000..903f08f327c
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f32-mf2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_0(
+ __riscv_vsetvlmax_e32m1,
+ vfloat32mf2_t,
+ vfloat64m1_t,
+ __riscv_vle32_v_f32mf2,
+ __riscv_vle64_v_f64m1,
+ __riscv_vfwsub_wv_f64m1,
+ __riscv_vse64_v_f64m1,
+ vfwsub_wv,
+ LOOP_WIDEN_BINARY_BODY_X16)
+
+/* The narrow source has EMUL < 1, thus the widened destination register
+ group must not overlap it at all. */
+/* { dg-final { scan-assembler-not
{vfwsub\.wv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */
--
2.43.0
