> From: Pan Li <[email protected]> > > The function riscv_v_widen_non_overlap_constraint_ok returns false > when the mode of the register is the same as the reference one. But > the LRA takes the inner reg of the subreg as the reference register, > for example the vs1 of the vfwsub.wv comes from the vget of the vd > register group as below. > > (minus:RVVM4DF (reg/v:RVVM4DF 151) > (float_extend:RVVM4DF (subreg:RVVM2SF (reg/v:RVVM4DF 139) [32, 32]))) > > Then the vs2 in RVVM4DF will always be rejected by the Wn4 constraint > because the reference mode is RVVM4DF as well, and result in the ICE > as below. > > during RTL pass: reload > internal compiler error: in lra_split_hard_reg_for, at > lra-assigns.cc:1908 > > Thus, remove the mode check and only take the register group overlap > into account for the non-overlap constraint.
This seems a bit counter-intuitive and I would rather see the subreg in the constraint function. Maybe I'm passing the wrong reg somewhere in lra? My guess is the subreg handling is inconsistent. Going to have a look, but after Cauldron. -- Regards Robin
