[PATCH v1 0/4] RISC-V: Allow RVV register overlap for vfwsub.wv

[pan2 . li]

From: Pan Li <pan2...@intel.com>

Like v[sz]ext.vf8, we continue the support for vfwsub.wv.

The below test suites are passed for this patch:
1. The rv64gcv fully regression tests.

Pan Li (4):
  RISC-V: Allow RVV register overlap for vfwsub.wv
  RISC-V: Add test cases for vfwsub.wv reg overlap
  RISC-V: Fix ICE for vfw{add,sub}.wv when vs1 is subreg of vd
  RISC-V: Add one more test case for vfwsub.wv

 gcc/config/riscv/riscv-v.cc                   |  2 +-
 gcc/config/riscv/vector.md                    | 20 +++---
 .../autovec/group_overlap/vfwsub_wv-f16-m1.c  | 20 ++++++
 .../autovec/group_overlap/vfwsub_wv-f16-m2.c  | 20 ++++++
 .../autovec/group_overlap/vfwsub_wv-f16-m4.c  | 20 ++++++
 .../autovec/group_overlap/vfwsub_wv-f16-mf2.c | 19 ++++++
 .../autovec/group_overlap/vfwsub_wv-f16-mf4.c | 19 ++++++
 .../autovec/group_overlap/vfwsub_wv-f32-m1.c  | 20 ++++++
 .../autovec/group_overlap/vfwsub_wv-f32-m2.c  | 20 ++++++
 .../autovec/group_overlap/vfwsub_wv-f32-m4.c  | 20 ++++++
 .../autovec/group_overlap/vfwsub_wv-f32-mf2.c | 19 ++++++
 .../gcc.target/riscv/rvv/base/pr112431-60.c   | 61 +++++++++++++++++++
 12 files changed, 249 insertions(+), 11 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-m1.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-m2.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-m4.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-mf2.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f16-mf4.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f32-m1.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f32-m2.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f32-m4.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwsub_wv-f32-mf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-60.c

-- 
2.43.0